AS6UA51216-55TI [ALSC]
Standard SRAM, 512KX16, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;
| 型号： | AS6UA51216-55TI |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 512KX16, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
June 2000
AS6UA51216
1.65V to 3.6V 512K×16 Intelliwatt™ low power CMOS SRAM with one chip enable
• Low power consumption: STANDBY
- 72 µW max at 3.6V
Features
• AS6UA51216
- 41 µW max at 2.7V
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 524,288 words × 16 bits
• 2.7V to 3.6V at 55 ns
• 2.3V to 2.7V at 70 ns
• 1.65V to 2.3V at 100 ns
- 28 µW max at 2.3V
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
- 28 mW at 2.3 V and 100 ns
Logic block diagram
Pin arrangement (top view)
44-pin 400-mil TSOP II
A0
A1
A2
V
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
DD
2
A6
A2
3
A7
512K × 16
A3
V
SS
A1
4
OE
A4
Array
(8,388,608)
A0
5
UB
A6
CS
6
LB
A7
A8
I/ O16
I/ O15
I/ O14
I/ O13
I/ O1
I/ O2
I/ O3
I/ O4
7
8
A12
A13
9
10
11
12
13
14
15
16
17
V
V
CC
SS
CC
I/ O1–I/ O8
I/ O9–I/ O16
I/ O
Control circuit
V
V
SS
buffer
I/ O5
I/ O6
I/ O7
I/ O12
I/ O11
I/ O10
I/ O9
A8
Column decoder
WE
I/ O
8
WE
A18
A17
A16
A15
A14
1
8
A9
19
20
21
22
A10
A11
UB
OE
LB
CS
A12
A13
Note: A “MODE” pad is to be placed between pins 33 and 34 and 11 and 12,
shorted. The bonding of this pad to V or V configures the device. There should
CC SS
only be 44+2+2 pads on the chip. Two extra V to separate out Array from
CC
Peripheral and Two-Mode Pads.
48-CSP Ball-Grid-Array Package
1
2
3
4
5
6
A
B
C
D
E
LB
OE
A0
A3
A1
A4
A2
NC
I/ O9 UB
CS I/ O1
I/ O10 I/ O11 A5
VSS I/ O12 A17
A6 I/ O2 I/ O3
A7 I/ O4 VCC
VCC I/ O13 VSS A16 I/ O5 VSS
I/ O15 I/ O14 A14 A15 I/ O6 I/ O7
I/ O16 NC A12 A13 WE I/ O8
F
G
H
A18
A8
A9
A10 A11
NC
Selection guide
VCC Range
Power Dissipation
Operating (ICC1
)
Standby (ISB2)
Min
(V)
Typ2
(V)
Max
Speed
(ns)
Product
(V)
3.6
2.7
2.3
Max (mA)
Max (µA)
AS6UA51216
AS6UA51216
AS6UA51216
2.7
2.3
3.0
2.5
2.0
55
70
2
1
1
20
15
12
1.65
100
6/ 27/ 00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS6UA51216
Functional description
The AS6UA51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t , t , t ) of 55/ 70/ 100 ns are ideal for low-power applications. Active high and low chip enables
AA RC WC
(CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA51216 is guaranteed not to exceed 72 µW power
consumption at 3.6V and 55ns; 41 µW at 2.7V and 70 ns; or 28 µW at 2.3V and 100 ns. The device also returns data when V is reduced
CC
to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/ or LB low. Data on the input pins I/ O1–
O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/ O
pins only after outputs have been disabled with output enable ( OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip
drives I/ O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/ O1–I/ O8, and UB controls the higher bits, I/ O9–I/ O16.
All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. Device is available in the JEDEC
standard 400-mL, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
–0.5
–0.5
–
Max
Unit
V
Voltage on VCC relative to V
V
VCC + 0.5
SS
tIN
Voltage on any I/ O pin relative to GND
Power dissipation
V
V
tI/ O
PD
1.0
+150
+125
20
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
Tbias
IOUT
–65
–55
–
°C
°C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Supply
CS
H
L
WE
X
OE
X
LB
X
H
X
L
UB
X
H
X
H
L
Current I/ O1–I/ O8 I/ O9–I/ O16
Mode
ISB
High Z
High Z
Standby (ISB)
X
X
L
H
H
ICC
High Z
DOUT
High Z
High Z
DOUT
Output disable (ICC)
L
L
H
L
L
H
L
ICC
High Z
DOUT
Read (ICC)
Write (ICC)
L
DOUT
L
H
L
D
High Z
IN
X
H
L
ICC
High Z
D
IN
L
D
D
IN
IN
Key: X = Don’t care, L = Low, H = High.
2
ALLIANCE SEMICONDUCTOR
6/ 27/ 00
AS6UA51216
Recommended operating condition (over the operating range)
Parameter
Description
Test Conditions
Min
2.4
2.0
1.5
Max
Unit
V
IOH = –2.1mA
OH = –0.5mA
OH = –0.1mA
IOL = 2.1mA
OL = 0.5mA
OL = 0.1mA
VCC = 2.7V
V
Output HIGH Voltage
I
VCC = 2.3V
VCC = 1.65V
VCC = 2.7V
VCC = 2.3V
VCC = 1.65V
VCC = 2.7V
OH
I
0.4
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
I
0.4
V
V
V
OL
I
0.2
2.2
2.0
VCC + 0.5
V
V
CC = 2.3V
CC = 1.65V
VCC = 2.7V
CC = 2.3V
CC = 1.65V
GND < VIN < VCC
VCC + 0.3
IH
V
1.4
VCC + 0.3
–0.5
–0.3
–0.3
–1
0.8
V
V
0.6
IL
V
0.4
IIX
Input Load Current
Output Load Current
+1
µA
µA
IOZ
GND < V < VCC; Outputs High Z
–1
+1
O
VCC = 3.6V
2
CS = V , VIN = V
IL
IL
VCC Operating Supply
Current
ICC
or V , IOUT = 0mA,
V
CC = 2.7V
CC = 2.3V
VCC = 3.6V
CC = 2.7V
CC = 2.3V
VCC = 3.6V (55/ 70/ 100 mS)
1
mA
mA
mA
µA
IH
f = 0
V
1
4
CS < 0.2V, V < 0.2V
IN
ICC1
@
Average VCC Operating
Supply Current at 1 MHz
or VIN > VCC – 0.2V,
f = 1 mS
V
2
2
1 MHz
V
40/ 30/ 20
30/ 25/ 15
25/ 10/ 12
100
Average VCC Operating CS ≠ V , V = V or
IL IN
IL
ICC2
V
CC = 2.7V (55/ 70/ 100 mS)
Supply Current
V , f = fMax
IH
V
CC = 2.3V(55/ 70/ 100 mS)
VCC = 3.6V
VCC = 2.7V
CS > VIH or UB = LB
> V , other inputs =
CS Power Down Current;
TTL Inputs
ISB
100
IH
V or V , f = 0
IL
IH
V
CC = 2.3V
VCC = 3.6V
CC = 2.7V
CC = 2.3V
100
CS > VCC – 0.2V or
CS Power Down Current; UB = LB > VCC – 0.2V
20
V
15
ISB1
µA
µA
CMOS Inputs
other inputs = 0V –
VCC, f = fMax
V
12
CS > VCC – 0.1V,
UB = LB = VCC – 0.1V
f = 0
ISBDR
Data Retention
VCC = 1.2V
2
Capacitance (f = 1 MHz, T = Room temperature, V = NOMINAL)
a
CC
Signals
Parameter
Symbol
Test conditions
IN = 0V
IN = VOUT = 0V
Max
5
Unit
pF
Input capacitance
C
A, CS, WE, OE, LB, UB
I/ O
V
IN
I/ O capacitance
C
V
7
pF
I/ O
6/ 27/ 00
ALLIANCE SEMICONDUCTOR
3
AS6UA51216
Read cycle (over the operating range)
–55
–70
–100
Parameter
Read cycle time
Symbol
tRC
Min
55
–
Max
–
Min
70
–
Max
–
Min
100
–
Max
–
Unit
ns
Notes
Address access time
tAA
55
55
70
70
100
100
ns
3
3
Chip enable (CS) access time
tACS
–
–
–
ns
Output enable (OE) access
time
tOE
tOH
–
25
–
–
35
–
–
50
–
ns
ns
Output hold from address
change
10
10
15
5
CS
o output in low Z
tCLZ
tCHZ
tOLZ
tBA
10
0
–
20
–
10
0
–
20
–
10
0
–
20
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
CS high to output in high Z
OE low to output in low Z
UB/ LB access time
5
5
5
–
55
–
–
70
–
–
100
–
UB/ LB low to low Z
UB/ LB high to high Z
OE high to output in high Z
Power up time
tBLZ
tBHZ
tOHZ
tPU
10
0
10
0
10
0
4, 5
4, 5
4, 5
4, 5
4, 5
20
20
–
20
20
–
20
20
–
0
0
0
0
0
0
Power down time
tPD
–
55
–
70
–
100
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input
Falling input
Undefined/ don’t care
Read waveform 1 (address controlled)
t
RC
Address
t
AA
t
t
OH
OH
D
Previous data valid
Data valid
OUT
Read waveform 2 (CS, OE, UB, LB controlled)
t
RC
Address
t
AA
OE
CS
t
OE
t
t
OH
OLZ
t
OHZ
BHZ
t
ACS
t
t
HZ
LZ
LB, UB
t
t
BA
t
BLZ
D
Data valid
OUT
4
ALLIANCE SEMICONDUCTOR
6/ 27/ 00
AS6UA51216
Write cycle (over the operating range)
–55
–70
–100
Parameter
Write cycle time
Symbol
tWC
tCW
tAW
Min
55
40
40
0
Max
–
Min
70
60
60
0
Max
–
Min
100
80
80
0
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
Chip enable to write end
Address setup to write end
Address setup time
–
–
–
–
–
–
tAS
–
–
–
12
Write pulse width
tWP
tAH
tDW
tDH
35
0
–
55
0
–
70
0
–
Address hold from end of write
Data valid to write end
Data hold time
–
–
–
25
0
–
30
0
–
40
0
–
–
–
–
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
UB/ LB low to end of write
tWZ
tOW
tBW
0
20
–
0
20
–
0
20
–
5
5
5
35
–
55
–
70
–
Shaded areas indicate preliminary information.
Write waveform 1 (WE controlled)
Address
t
t
WC
t
AH
CW
CS
t
BW
LB, UB
t
AW
t
t
WP
AS
WE
t
t
DH
DW
Data valid
D
IN
t
WZ
t
OW
D
Data undefined
OUT
High Z
Write waveform 2 (CS controlled)
t
WC
Address
t
t
AS
AH
t
CW
CS
t
AW
t
BW
LB, UB
WE
t
WP
t
t
DH
DW
Data valid
High Z
D
IN
t
t
CLZ
WZ
t
OW
D
Data undefined
OUT
High Z
6/ 27/ 00
ALLIANCE SEMICONDUCTOR
5
AS6UA51216
Data retention characteristics (over the operating range)
Parameter
Symbol
Test conditions
Min
1.2V
–
Max
3.6
2
Unit
V
V
CC for data retention
VDR
VCC = 1.2V
CS ≥ VCC – 0.1V or
UB = LB = > VCC – 0.1V
Data retention current
ICCDR
tCDR
tR
mA
ns
Chip deselect to data retention time
Operation recovery time
0
–
V
≥ VCC – 0.1V or
IN
V
≤ 0.1V
tRC
–
ns
IN
Data retention waveform
Data retention mode
1.2V
V
V
V
CC
V
≥
CC
CC
DR
t
t
R
CDR
V
DR
V
V
IH
CS
IH
AC test loads and waveforms
Thevenin equivalent:
R1
R1
V
R
CC
V
TH
CC
V
OUTPUT
OUTPUT
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
V
Typ
R2
CC
R2
90%
10%
90%
10%
INCLUDING
JIG AND
INCLUDING
JIG AND
SCOPE
< 5 ns
(c)
GND
(a)
SCOPE
(b)
Parameters
VCC = 3.0V
1105
VCC = 2.5V
16670
15380
8000
VCC = 2.0V
15294
Unit
R1
R2
Ohms
Ohms
Ohms
Volts
1550
11300
RTH
645
6500
V
1.75V
1.2V
0.85V
TH
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
and t are specified with C = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WEis HIGH for read cycle.
CSand OE are LOW for read cycle.
Address valid prior to or coincident with CS transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/ A.
13 1.2V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
6
ALLIANCE SEMICONDUCTOR
6/ 27/ 00
AS6UA51216
Typical DC and AC characteristics
Normalized supply current
vs. supply voltage
1.4
Normalized access time
vs. supply voltage
Normalized standby current
vs. ambient temperature
1.0
3.0
2.5
2.0
1.2
V
= V typ
CC
IN
V
= V typ
CC
CC
1.0
0.8
0.6
0.4
0.2
0.0
0.75
0.5
T = 25
°
C
A
V
= V typ
IN
CC
1.5
1.0
0.5
T = 25° C
A
0.0
0.25
0.0
-0.5
1.7
2.2
2.7
3.2
3.7
1.7
2.2
2.7
3.2
3.7
-55
25
Ambient temperature (°C)
105
Supply voltage (V)
Supply Voltage (V)
Normalized standby current
vs. supply voltage
Normalized I
CC
vs. cycle time
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.5
1.0
I
SB2
V
= 3.6V
T = 25° C
CC
A
0.50
0.10
V
= V typ
CC
IN
T = 25° C
A
1
5
10
15
2.8
1.9
Supply voltage (V)
1
3.7
Supply voltage (V)
Package diagrams and dimensions
44-pin TSOP II
c
44 43 42 41 40 39 38 37 36 35 34 33 32 3130 29 28 27 26 25 24 23
Min
Max
(mm)
(mm)
A
1.2
H
e
44-pin TSOP II
e
A
0.05
0.95
0.25
1
A
1.05
0.45
2
b
21 22
1
2
3
4
5
6
7
8
9
10 11 12 13 1415 16 17 18 19 20
c
d
0.15 (typical)
d
20.85
10.06
11.56
21.05
10.26
11.96
e
l
A
2
A
0–5°
He
E
l
A
1
0.80 (typical)
0.40 0.60
E
b
6/ 27/ 00
ALLIANCE SEMICONDUCTOR
7
AS6UA51216
48-ball FBGA
Top View
Bottom View
Ball # A1 Index
6
5
4
3
2
1
Ball # A1
A
B
SRAM Die
C
D
E
C1
C
F
A
G
H
Elastomer
A
B
B1
Detail View
A
Side View
D
Ε2
Ε
E2
Y
E
Die
Die
Ε1
0.3/ Typ
Minimum
Typical
0.75
7.00
3.75
8.5
Maximum
A
B
–
6.90
–
–
Notes
7.10
–
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
B1
C
8.4
–
8.6
–
C1
D
5.25
0.35
–
4. All tolerance are ± 0.050 unless otherwise specified.
5. Typ: typical.
0.30
–
0.40
1.20
–
E
6. Y is coplanarity: 0.08 (max).
E1
E2
Y
–
0.68
0.25
–
0.22
–
0.27
0.08
8
ALLIANCE SEMICONDUCTOR
6/ 27/ 00
AS6UA51216
Ordering codes
Ordering Code
AS6UA51216-TC
AS6UA51216-BC
AS6UA51216-TI
AS6UA51216-BI
Package Type
44-pin TSOP II
Speed (ns)
Operating Range
Commercial
48-ball fine pitch BGA
44-pin TSOP II
55/ 70/ 100
Industrial
48-ball fine pitch BGA
Part numbering system
AS6UA
51216
Device number
B, T
C, I
Package:
T: TSOP II
B: CSP BGA
Temperature range:
C: Commercial: 0° C to 70° C
I: Industrial: –40° C to 85° C
SRAM Intelliwatt™ prefix
6/ 27/ 00
ALLIANCE SEMICONDUCTOR
9
Copyright ©2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of
their respective companies. Alliance reserves the right to make changes to thisweb site and its products at any time withoutnotice. Alliance assumes no responsibility for any errors that may appear in thisweb site. Alliance does not
assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement
of any intellectual property rights, except as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of
Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not
authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-
supporting systems implies that themanufacturer assumes all risk of such use andagrees to indemnify Alliance against all claims arising from such use.
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