AS7C1024-12TC 概述
5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) 5V / 3.3V 128K ×8 CMOS SRAM (进化引脚)
AS7C1024-12TC 数据手册
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PDF下载November 2000
AS7C1024
AS7C31024
®
5V/ 3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
Features
• AS7C1024 (5V version)
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• AS7C31024 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 10/ 12/ 15/ 20 ns address access time
- 5/ 6/ 8/ 10 ns output enable access time
• Low power consumption: ACTIVE
- 825 mW (c) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
• TTL/ LVTTL-compatible, three-state I/ O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOPI
- 8 × 13.4 mm sTSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
32-pin TSOP I
(8 x 20mm)
V
CC
GND
A11
A9
1
OE
A10
CE1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
V
A15
CE2
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/ O0
I/ O1
I/ O2
GND
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CC
2
Input buffer
3
A8
4
A13
WE
CE2
A15
I/ O7
I/ O6
I/ O5
I/ O4
I/ O3
GND
I/ O2
I/ O1
I/ O0
A0
5
WE
A13
6
A0
A1
A2
A3
A4
A5
A6
A7
A8
7
A8
I/ O7
I/ O0
8
V
A9
CC
9
NC
A16
A14
A12
A7
A11
512
×256×8
10
11
12
13
14
15
16
9
OE
A10
Array
(1,048,576)
10
11
12
13
14
15
16
CE1
I/ O7
I/ O6
I/ O5
I/ O4
I/ O3
A6
A1
18
17
A5
A2
A4
A3
WE
Column decoder
Control
circuit
OE
CE1
CE2
Selection guide
AS7C1024-12 AS7C1024-15 AS7C1024-20
AS7C31024-12 AS7C31024-15 AS7C31024-20 Unit
AS7C1024-10
AS7C31024-10
Maximum address access time
Maximum output enable access time
10
5
12
6
15
8
20
10
ns
ns
AS7C1024
AS7C31024
AS7C1024
AS7C31024
150
100
10
140
90
10
10
125
80
10
10
110
75
15
mA
mA
mA
mA
Maximum operating current
Maximum CMOS standby current
10
15
Shaded areas contain advance information.
11/ 29/ 00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS7C1024
AS7C31024
®
Functional description
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 131,072 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/ 12/ 15/ 20 ns with output enable access times (tOE) of 5/ 6/ 8/ 10 ns
are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with
multiple-bank systems.
When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume I power.
SB
If the bus is static, then full standby power is reached (ISB1 or ISB2). For example, the AS7C31024 is guaranteed not to exceed
0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/ O0-
I/ O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid
bus contention, external devices should drive I/ O pins only after outputshave been disabled with output enable ( OE) or write
enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.
The chips drive I/ O pins with the data word referenced by the input address. When either chip enable is inactive, output
enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter
Symbol
Min
–0.50
-0.50
–0.50
–
Max
+7.0
Unit
V
AS7C1024
V
t1
Voltage on VCC relative to GND
AS7C31024
V
+5.0
V
t1
Voltage on any pin relative to GND
Power dissipation
V
VCC +0.50
1.0
V
t2
PD
W
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Tstg
–65
–55
–
+150
+125
20
°C
°C
mA
Tbias
IOUT
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE1
H
X
L
CE2
X
WE
X
OE
X
Data
Mode
High Z
High Z
High Z
DOUT
Standby (ISB, ISB1
Standby (ISB, ISB1
)
)
L
X
X
H
H
H
Output disable (ICC)
Read (ICC)
L
H
H
L
L
H
L
X
D
Write (ICC)
IN
Key: X = Don’t Care, L = Low, H = High
2
ALLIANCE SEMICONDUCTOR
11/ 29/ 00
AS7C1024
AS7C31024
®
Recommended operating conditions
Parameter
Device
Symbol
VCC
Min
4.5
3.0
2.2
2.0
–0.5
0
Nominal
Max
5.5
Unit
V
AS7C1024
AS7C31024
AS7C1024
AS7C31024
5.0
3.3
–
Supply voltage
VCC
3.6
V
V
VCC + 0.5
VCC + 0.5
0.8
V
IH
Input voltage
V
–
V
IH
†
V
–
V
IL
commercial
industrial
TA
TA
–
70
°C
°C
Ambient operating temperature
–40
–
85
†
V min = –3.0V for pulse width less than t
IL
.
RC/ 2
DC operating characteristics (over the operating range)
-10
-12
-15
-20
Unit
Parameter
Sym
Test conditions
Device
Min Max Min Max Min Max Min Max
Input leakage
current
| ILI| VCC = Max, VIN = GND to VCC
–
–
1
1
–
–
1
1
–
–
1
1
–
–
1
1
µA
µA
Output leakage
current
VCC = Max, CE1 = VIH or
| ILO|
CE2 = V , VOUT = GND to V
IL
CC
Operating
power supply
current
VCC = Max, CE1 = V ,
AS7C1024
–
–
–
–
–
–
150
100
80
–
–
–
–
–
–
140
90
75
50
10
10
–
–
–
–
–
–
125
80
65
40
10
10
–
–
–
–
–
–
110
75
60
35
15
15
IL
ICC CE2 = V , f = fMax, IOUT = 0
mA
mA
mA
IH
AS7C31024
mA
VCC = Max, CE1 ≥ VIH and/ or AS7C1024
ISB CE2 ≤ V , V = VIH or V ,
IL IN
IL
AS7C31024
60
f = fMax, IOUT = 0mA
Standby power
supply current
VCC = Max, CE1 ≥ VCC–0.2V AS7C1024
10
ISB1
V
≤ GND + 0.2V or
≥ VCC –0.2V, f = 0
IN
AS7C31024
10
V
IN
V
IOL = 8 mA, VCC = Min
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
OL
Output voltage
V
IOH = –4 mA, VCC = Min
2.4
2.4
2.4
2.4
OH
Shaded areas contain advance information.
Capacitance (f = 1 MHz, T = 25 °C, V = NOMINAL)
a
CC
Symbol
Parameter
Signals
Test conditions
IN = 0V
VIN = VOUT = 0V
Max
Unit
Input capacitance
I/ O capacitance
C
A, CE1, CE2, WE, OE
I/ O
V
5
7
pF
pF
IN
C
I/ O
11/ 29/ 00
ALLIANCE SEMICONDUCTOR
3
AS7C1024
AS7C31024
®
Read cycle (over the operating range)
-10
-12
-15
-20
Parameter
Read cycle time
Symbol Min Max Min Max Min Max Min Max Unit
Notes
tRC
tAA
10
–
–
–
–
2
3
3
–
–
0
–
0
–
–
10
10
10
3
12
–
–
–
–
3
3
3
–
–
0
–
0
–
–
12
12
12
3
15
–
–
–
–
3
3
3
–
–
0
–
0
–
–
15
15
15
4
20
–
–
–
–
3
3
3
–
–
0
–
0
–
–
20
20
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
3
Chip enable (CE1) access time
Chip enable (CE2) access time
Output enable (OE) access time
Output hold from address change
CE1 Low to output in low Z
CE2 High to output in low Z
CE1 Low to output in high Z
CE2 Low to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
tACE1
tACE2
tOE
3, 12
3, 12
tOH
–
–
–
–
5
tCLZ1
tCLZ2
tCHZ1
tCHZ2
tOLZ
tOHZ
tPU
–
–
–
–
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
–
–
–
–
3
3
4
5
3
3
4
5
–
–
–
–
3
3
4
5
4, 5
–
–
–
–
4, 5, 12
4, 5, 12
Power down time
tPD
10
12
15
20
Key to switching waveforms
Rising input
Falling input
Undefined / don’t care
Read waveform 1 (address controlled)
t
RC
Address
t
t
AA
OH
D
Data valid
OUT
Read waveform 2 (CE1, CE2, and OE controlled)
t
RC1
CE1
CE2
OE
t
OE
t
t
OHZ
OLZ
t
, t
CHZ1 CHZ2
t
,
ACE1 tACE2
D
OUT
Data valid
t
, t
CLZ1 CLZ2
t
PD
I
CC
t
PU
Current
supply
I
50%
50%
SB
4
ALLIANCE SEMICONDUCTOR
11/ 29/ 00
AS7C1024
AS7C31024
®
Write cycle (over the operating range)
-10
-12
-15
-20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max Unit
Notes
tWC
tCW1
tCW2
tAW
tAS
10
9
9
9
0
7
0
6
0
–
3
–
–
–
–
–
–
–
–
–
5
–
12
10
10
10
0
–
–
–
–
–
–
–
–
–
5
–
15
12
12
12
0
–
–
–
–
–
–
–
–
–
5
–
20
12
12
12
0
–
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable (CE1) to write end
Chip enable (CE2) to write end
Address setup to write end
Address setup time
12
12
12
Write pulse width
tWP
tAH
tDW
tDH
tWZ
tOW
8
9
12
0
Address hold from end of write
Data valid to write end
0
0
6
9
10
0
Data hold time
0
0
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
Shaded areas contain advance information.
–
–
–
3
3
3
Write waveform 1 ( WE controlled)
t
WC
t
t
t
t
AW
AH
DH
Address
WE
WP
t
AS
t
DW
D
Data valid
IN
t
t
WZ
OW
D
OUT
Write waveform 2 (CE1 and CE2 controlled)
t
WC
t
t
AH
AW
Address
t
t
, t
AS
CW1 CW2
CE1
CE2
t
WP
WE
t
t
t
DH
WZ
DW
D
Data valid
IN
D
OUT
11/ 29/ 00
ALLIANCE SEMICONDUCTOR
5
AS7C1024
AS7C31024
®
Data retention characteristics (over the operating range)
Parameter
Symbol
Test conditions
Device
Min
2.0
–
Max
–
Unit
V
V
CC for data retention
VDR
VCC = 2.0V
AS7C1024
5
mA
mA
ns
Data retention current
ICCDR
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
AS7C31024
–
1
Chip deselect to data retention time
Operation recovery time
tCDR
tR
0
–
V
≥ VCC–0.2V or
IN
V
≤ 0.2V
tRC
–
–
ns
IN
Input leakage current
| ILI |
1
µA
Data retention waveform
Data retention mode
2.0V
V
V
V
≥
V
CC
CC
CC
DR
t
t
R
CDR
V
DR
V
V
IH
CE1
IH
AC test conditions
– 5V output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
Thevenin equivalent:
168W
D
+1.728V (5V and 3.3V)
OUT
– Input and output timing reference levels: 1.5V.
+5V
+3.3V
480W
320W
D
D
OUT
OUT
+3.0V
90%
10%
90%
10%
255W
C(14)
GND
255W
C(14)
GND
2 ns
Figure A: Input pulse
GND
Figure B: 5V Output load
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE1 is required to meet I specification.
CC CC SB
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
t
and t are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
CHZ
CLZ
This parameter is guaranteed, but not 100% tested.
WEis High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 2V data retention applies to commercial temperature operating range only.
14 C=30pF, except all high Z and low Z parameters, C=5pF.
6
ALLIANCE SEMICONDUCTOR
11/ 29/ 00
AS7C1024
AS7C31024
®
Typical DC and AC characteristics
Normalized supply current I , I
Normalized supply current I , I
Normalized supply current I
SB1
CC SB
CC SB
vs. supply voltage V
vs. ambient temperatureT
vs. ambient temperature T
a
CC
a
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
625
25
VCC = V (NOMINAL)
I
I
CC
CC
CC
5
1
I
I
SB
SB
0.2
0.04
MIN
NOMINAL
–55
–10
Ambient temperature (°C)
Normalized access time t
35
80
-55
-10
Ambient temperature (°C)
Normalized supply current I
CC
35
80
MAX
125
125
Supply voltage (V)
Normalized access time t
vs. supply voltage V
AA
AA
CC
vs. ambient temperatureT
vs. cycle frequency 1/ t , 1/ t
a
RC
WC
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VCC = VCC(NOMINAL)
T = 25° C
T = 25° C
VCC = VCC(NOMINAL)
a
a
MIN
NOMINAL
–55
–10
Ambient temperature (°C)
Output sink current I
35
80
0
25
Cycle frequency (MHz)
Typical access time change ∆t
AA
50
75
MAX
125
100
Supply voltage (V)
Output source current I
vs. output voltage V
OH
OH
OL
OL
vs. output voltage V
vs. output capacitive loading
140
120
100
80
140
120
100
80
35
30
25
20
15
10
5
VCC = VCC(NOMINAL)
VCC = VCC(NOMINAL)
VCC = VCC(NOMINAL)
T = 25° C
T = 25° C
a
a
60
60
40
40
20
20
0
0
0
0
0
0
250
500
750
V
V
1000
CC
CC
Output voltage (V)
Output voltage (V)
Capacitance (pF)
11/ 29/ 00
ALLIANCE SEMICONDUCTOR
7
AS7C1024
AS7C31024
®
Package dimensions
32-pin PDIP
A
Min
Max
0.180
-
0.055
0.021
0.012
1.571
0.325
0.295
D
B
S
A
A1
B
b
c
D
E
-
0.015
0.045
0.015
0.008
-
E
E1
L
A1
e
b
Seating
Plane
Pin 1
0.300
0.280
α
c
E1
e
eA
0.100 BSC
eA
L
a
0.330
0.110
0°
0.370
0.142
15°
D
S
-
0.043
B
e
32-pin SOJ 300 mil 32-pin SOJ 400 mil
A
E2
E1
A1
Min
-
A1 0.025
A2 0.086
Max
0.145
-
Min
-
Max
0.145
-
Seating
Plane
b
A
0.025
0.086
0.026
0.015
0.007
0.820
0.360
0.395
0.435
Pin 1
c
0.105
0.032
0.020
0.013
0.830
0.275
0.305
0.340
0.115
0.032
0.020
0.013
0.830
0.380
0.405
0.445
A2
B
b
c
D
E
0.026
0.014
0.006
0.820
0.250
E
b
e
E1 0.292
E2 0.330
e
0.050 BSC
0.050 BSC
α
32-pin TSOP 8×20
c
Min
–
Max
1.20
0.15
1.05
0.27
0.21
18.60
D
Hd
A2
A
A1
A
A1
A2
b
c
D
e
E
Hd
L
L
0.05
0.95
0.17
0.10
18.20
pin 1
pin 32
0.50 nominal
E
pin 16
pin 17
7.80
19.80
0.50
8.20
20.20
0.70
α
0°
5°
8
ALLIANCE SEMICONDUCTOR
11/ 29/ 00
AS7C1024
AS7C31024
®
Ordering codes
Package \ Access
Volt/ Temp
5V commercial
5V industrial
time
10 ns
AS7C1024-10TJC
NA
12 ns
15 ns
20 ns
AS7C1024-12TJC
AS7C1024-12TJI
AS7C1024-15TJC
AS7C1024-15TJI
AS7C31024-15TJC
AS7C31024-15TJI
AS7C1024-15JC
AS7C1024-15JI
AS7C31024-15JC
AS7C31024-15JI
AS7C1024-15TC
AS7C1024-15TI
AS7C31024-15TC
AS7C31024-15TI
AS7C1024-20TJC
AS7C1024-20TJI
AS7C31024-20TJC
AS7C31024-20TJI
AS7C1024-20JC
AS7C1024-20JI
AS7C31024-20JC
AS7C31024-20JI
AS7C1024-20TC
AS7C1024-20TI
AS7C31024-20TC
AS7C31024-20TI
Plastic SOJ, 300 mL
Plastic SOJ, 400 mL
3.3V commercial AS7C31024-10TJC AS7C31024-12TJC
AS7C31024-12TJI
AS7C1024-12JC
AS7C1024-12JI
AS7C31024-12JC
AS7C31024-12JI
AS7C1024-12TC
AS7C1024-12TI
AS7C31024-12TC
AS7C31024-12TI
3.3V industrial
5V commercial
5V industrial
NA
AS7C1024-10JC
NA
AS7C31024-10JC
3.3V commercial
3.3V industrial
5V commercial
5V industrial
NA
NA
NA
NA
NA
TSOP 8×20
3.3V commercial
3.3V industrial
NA: not available
Shaded areas contain advance information.
Part numbering system
AS7C
X
1024
–XX
X
X
Package: TP=PDIP 300 mil
T=TSOP 8×20
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
SRAM Blank=5V CMOS Device Access
prefix
3=3.3V CMOS number time
J=SOJ 400 mil
TJ=SOJ 300 mil
11/ 29/ 00
ALLIANCE SEMICONDUCTOR
9
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AS7C1024-12TC 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
AS7C1024-12TI | ALSC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) | 获取价格 | |
AS7C1024-12TJC | ALSC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) | 获取价格 | |
AS7C1024-12TJI | ALSC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) | 获取价格 | |
AS7C1024-12TPC | ETC | x8 SRAM | 获取价格 | |
AS7C1024-15 | ALSC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) | 获取价格 | |
AS7C1024-15HC | ALSC | Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32 | 获取价格 | |
AS7C1024-15HI | ALSC | Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32 | 获取价格 | |
AS7C1024-15JC | ALSC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) | 获取价格 | |
AS7C1024-15JI | ALSC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) | 获取价格 | |
AS7C1024-15PC | ETC | x8 SRAM | 获取价格 |
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