AS7C184098LL-70BI [ALSC]
Standard SRAM, 256KX16, 70ns, CMOS, PBGA48;
| 型号： | AS7C184098LL-70BI |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 256KX16, 70ns, CMOS, PBGA48 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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• Smallest footprint packages
- 48 ball FBGA
- 400 mil TSOP II
• Center power and ground pins for low noise
• ESD protection ≥ 2000 volts
• Organization: 262,144 words × 16 bits
• Intelliwatt™ active power reduction circuitry
• 1.65V to 1.95V operating range
• 35/ 55/ 70/ 100 ns address access time
• Low power consumption
• Latch-up current ≥ 200 mA
- Active: 40 mW max (100 ns cycle) 1.95 V
- Standby: 90 µW max
- Very low DC component in active power, 100 µA
• Individual byte read/ write controls
• 1.2V data retention
• Industrial temperature range available (-40 to +85 °C)
• Other voltage versions available
- 2.7V to 3.6V (AS7C34098LL)
- 2.3V to 3.0V (AS7C254098LL)
• Easy memory expansion with CE, OE inputs
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TSOP II
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
VDD
A0
A1
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
VSS
VDD
I/O11
I/O10
1024 × 256 × 16
V
SS
A2
3
A3
4
Array
A4
5
(4,194,304)
CE
6
I/O0
I/O1
I/O2
I/O3
VDD
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/ O0–I/ O7
I/ O8–I/ O15
I/ O
buffer
Control circuit
Column decoder
WE
I/O9
I/O8
NC
A14
A13
A12
A11
A10
A6
A7
A8
A9
UB
OE
LB
CE
48-CSP Ball-Grid-Array Package
1
2
3
4
5
6
A
B
C
D
E
LB
OE
UB
A
A
A
2
NC
0
1
I/ O
I/ O
A
A
CE
I/ O
I/ O
I/ O
8
9
3
4
0
2
I/ O
A
A
6
10
11
12
13
5
1
V
I/ O
I/ O
I/ O
A
A
I/ O
V
DD
SS
17
7
3
V
NC
A
I/ O
V
SS
DD
16
4
F
I/ O
A
A
I/ O
I/ O
I/ O
14
14
15
5
6
7
G
H
I/ O
NC
A
A
WE
15
12
13
NC
A
A
A
A
11
NC
8
9
10
6HOHFWLRQꢀJXLGH
-35
35
10
45
45
-55
55
10
28
45
-70
-100
100
10
Unit
ns
Maximum address access time
Maximum output enable access time
Maximum operating current
70
10
25
45
ns
20
mA
µA
Maximum CMOS standby current
45
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The AS7C184098LL is a high performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) organized as 262,144 words × 16
bits. It is designed for portable applications where fast data access, long battery life, low heat dissipation, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 35/ 55/ 70/ 100 ns are ideal for high performance applications. The chip enable input
CE permits easy memory expansion with multiple-bank memory systems.
When CE is High, or when UB and LB are simultaneously pulled High, the device enters standby mode. The AS7C184098LL is guaranteed
not to exceed 90 µW power consumption in CMOS standby mode. These devices also offer data retention down to 1.5V.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/ O0-I/ O15 is written on the
rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/ O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/ O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/ O0–I/ O7, and UB controls the higher bits, I/ O8–I/ O15.
This device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the
smallest possible footprint. This 48-ball JEDEC registered package has a ball pitch of 0.75 mm and external dimensions of 8mm × 6mm.
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CE
H
L
WE
X
OE
X
LB
X
H
X
L
UB
X
H
X
H
L
Supply current I/ O0–I/ O7
I/ O8–I/ O15 Mode
ISB
High Z
High Z
Standby
X
X
L
H
H
ICC
High Z
DOUT
High Z
High Z
DOUT
Output disable
Read
L
L
H
L
L
H
L
ICC
High Z
DOUT
L
DOUT
L
H
L
D
High Z
IN
X
H
L
ICC
High Z
D
Write
IN
L
D
D
IN
IN
Key: X = don’t care, L = Low, H = High
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Parameter
Symbol
Min
-0.5
-0.5
–
Max
Unit
V
Voltage on any input pin relative to V
V
+2.5
VDD + 0.5
1.0
SS
tIN
Voltage on any I/ O pin
Power dissipation
V
V
tI/ O
PD
W
Storage temperature (plastic)
DC output current
Tstg
Iout
-55
–
+150
20
oC
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
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Parameter
Symbol
VDD
Min
Typ
1.80
0.0
–
Max
Unit
V
1.65
0.0
1.95
Supply voltage
Input voltage
V
0.0
V
SS
V
0.7 × VDD
–0.5†
0
VDD + 0.5
0.3 × VDD
70
V
IH
V
–
V
IL
Commercial
Ambient operating temperature
Industrial
TA
TA
–
°C
°C
-40
–
85
†
V
min = –3.0V for pulse width less than 10 ns.
IL
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-35
-55
-70
-100
Min
Parameter
Symbol
| ILI
| ILO
Test conditions
Min
–
Max
1
Min
–
Max
1
Min
Max
1
Max Unit
Input leakage
current
|
0V ≤ V ≤ VDD
–
–
1
1
µA
µA
in
Output leakage
current
Outputs disabled
0V ≤ Vout ≤ VDD
|
–
–
1
0.2
–
–
–
1
0.2
–
–
–
1
0.2
–
–
–
IOL = 100 µA,
V
0.2
–
OL
V
DD = Min
IOH = –100 µA,
DD = Min
Output voltage
V
V
0.8 × VDD
0.8 × VDD
0.8 × VDD
0.8 × VDD
OH
V
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-35
-55
-70
-100
Min Max Unit
Parameter
Symbol Test conditions
Min
Max
Min
Max
28
Min
Max
CE ≤ V , VDD = Max,
IL
IDD
f = fMax = 1/ t
IOUT = 0
–
45
–
–
25
–
20
mA
RC,
Operating power
supply current
CE = V , VDD = Max, f = 0,
SS
IDD1
ISB
–
–
100
100
–
–
100
100
–
–
100
100
–
–
100
100
µA
µA
IOUT = 0
CE ≥ V , VDD = Max,
IH
f = fMax = 1/ tRC
Standby power
supply current
CE ≥ VDD–0.2V, VDD = Max,
V ≤ V + 0.2V or
ISB1
–
45
–
45
–
45
–
45
µA
in
SS
V ≥ VDD - 0.2V, f = 0
in
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Parameter
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Symbol
Signals
Test conditions
V = 0V
Max
5
Unit
pF
Input capacitance
I/ O capacitance
C
A, CE, WE, OE, LB, UB
I/ O
IN
in
C
V = Vout = 0V
7
pF
I/ O
in
Outputs disabled in all cases.
I
= worst case power consumption.
CC
I
= current for the disabled, bus-active condition.
SB
I
= enabled, bus-inactive condition.
CC1
I
= “full standby” or the disabled, bus-inactive condition.
SB1
I
= current in data retention (reduced VDD) mode.
CCDR
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-35
-55
-70
-100
Min
Parameter
Symbol
tRC
Min
35
–
Max
–
Min
55
–
Max
–
Min
70
–
Max
–
Max
–
Unit
ns
Notes
Read cycle time
Address access time
100
–
tAA
35
55
70
100
ns
3
3
Chip enable (CE) access
time
tACE
–
–
3
3
–
35
10
–
–
–
3
3
–
55
10
–
–
–
3
3
–
70
10
–
–
–
3
3
–
100
10
–
ns
ns
ns
ns
ns
Output enable (OE) access
time
tOE
Output hold from address
change
tOH
tCLZ
tCHZ
5
CE Low to output in
Low Z
–
–
–
–
4, 5
4, 5
4, 5
CE High to output in High
Z
10
10
10
10
OE Low to output in
Low Z
tOLZ
tBA
3
–
3
–
10
–
3
–
3
–
10
–
3
–
3
–
10
–
3
–
3
–
10
–
ns
ns
ns
Byte select access time
Byte select Low to
Low Z
tBLZ
4,5
4,5
4, 5
Byte select High to
High-Z
tBHZ
–
–
10
10
–
–
10
10
–
–
10
10
–
–
10
10
ns
ns
OE High to output in High
Z
tOHZ
Power up time
tPU
tPD
0
–
–
?
0
–
–
0
–
–
0
–
–
ns
ns
4, 5
4, 5
Power down time
55
70
100
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Rising input
Falling input
Undefined output/don’t care
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tRC
Address
tAA
tOH
tOH
Data out
Previous data valid
Data valid
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tRC
Address
OE
tAA
tOE
tOH
tOLZ
CE
tOHZ
tHZ
tACE
tLZ
LB, UB
Data out
tBA
tBHZ
tBLZ
Data valid
70
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35
55
100
Max Unit
Parameter
Symbol
tWC
Min
Max Min
Max Min
Max Min
Notes
12
Write cycle time
Chip enable to write end
35
15
15
0
–
–
–
–
–
55
15
15
0
–
–
–
–
–
70
15
15
0
–
–
–
–
–
100
15
15
0
–
–
–
–
–
ns
ns
ns
ns
ns
tCW
Address setup to write end tAW
Address setup time
Write pulse width
tAS
12
tWP
15
15
15
15
Address hold from end of
write
tAH
0
–
0
–
0
–
0
–
ns
Data valid to write end
Data hold time
tDW
tDH
10
0
–
–
10
0
–
–
10
0
–
–
10
0
–
–
ns
ns
4, 5
4, 5
Write enable to output in
High Z
tWZ
tOW
tBW
–
1
5
–
–
–
1
5
–
–
–
1
5
–
–
–
1
5
–
–
ns
ns
ns
Output active from write
end
4, 5
Byte Select Low to end of
write
15
15
15
15
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tWC
Address
tWR
tCW
tBW
tAW
CE
LB, UB
tAS
tWP
WE
Data in
tDW
tDH
Data valid
tWZ
tOW
High Z
Data out
Data undefined
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tWC
Address
tAS
tWR
tCW
CE
tAW
tBW
LB, UB
WE
tWP
tDH
tDW
Data valid
Data in
tWZ
Data undefined
tOW
tCLZ
Data out
High Z
High Z
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Parameter
Symbol
VDR
Test conditions
VDD = 1.5V
Min
1.2
–
Max
–
Unit
V
Notes
VDD for data retention
Data retention current
ICCDR
15
–
µA
ns
5
5
5
CE ≥ VDD–0.2V
Chip deselect to data retention time tCDR
0
V ≥ VDD–0.2V or
in
V ≤ 0.2V
Operation recovery time
tR
tRC
–
ns
in
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Data retention mode
VDD
1.65V
VIH
1.65V
VIH
V
DR ≥ 1.2V
tCDR
tR
VDR
CE
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- Output load: see Figure B, except as noted.
Thevenin Equivalent:
- Input pulse level: V to VDD. See Figure A.
- Input rise and fall times: 5 ns. See Figure A.
SS
5700Ω
Dout
- Input and output timing reference levels: 0.5 × VDD.
VDD
VDD
13,300Ω
13,300Ω
Dout
Dout
1.8V
90%
10%
90%
10%
10,000Ω
30 pF*
VSS
10,000Ω
5 pF*
VSS
*including scope
and jig capacitance
2ns
Figure A: Input pulse
V
SS
Figure B: Output load
Figure C: Output load for tCLZ, tCHZ,
tOLZ, tOHZ, tOW, tWZ, tBLZ, tBHZ
1RWHV
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE is required to meet I specification.
DD DD SB
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
These parameters are specified with C = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
L
This parameter is guaranteed but not tested.
WEis High for read cycle.
CEand OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
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44-pin TSOP II
c
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Min (mm) Max (mm)
A
–
1.2
–
A
0.05
0.95
0.30
1
He
E
44-pin TSOP II
A
1.05
0.45
2
b
c
D
E
He
e
0.127 (typical)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
18.28
10.03
11.56
18.54
10.29
11.96
D
l
A2
0.80 (typical)
A
0–5°
l
0.40
0.60
A1
b
e
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Bottom View
Side View
Top View
6
5
4
3
2
1
Ball #A1 index
Ball #A1
A
B
C
D
E
B1
B
D
F
C
G
H
C
E1
A1
E
A
Minimum
Typical
6.00
3.75
8.00
5.25
0.75
0.35
-
Maximum
A
A1
B
5.90
6.10
-
-
Detail View
Notes
1. Units: mm
7.90
8.10
B1
C
-
-
C
2. Pitch: (x,y)=0.75 mm × 0.75 mm (typ.)
3. Y is coplanarity: 0.10 mm
-
-
-
E1
Y
D
-
E
E
-
0.17
-
1.20
0.27
-
E1
Y
0.22
0.10
0 $ 5 6
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Package \ Access time
35 ns
55 ns
70 ns
100 ns
AS7C184098LL-35TC
AS7C184098LL-35TI
AS7C184098LL-35BC
AS7C184098LL-35BI
AS7C184098LL-55TC
AS7C184098LL-55TI
AS7C184098LL-55BC
AS7C184098LL-55BI
AS7C184098LL-70TC
AS7C184098LL-70TI
AS7C184098LL-70BC
AS7C184098LL-70BI
AS7C184098LL-100TC
AS7C184098LL-100TI
AS7C184098LL-100BC
AS7C184098LL-100BI
TSOP II
CSP BGA
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LL
AS7C
18
4098
–XX
X
C
3=3.3V CMOS
SRAM prefix 25=2.5V CMOS
18=1.8V CMOS
Temperature range,
C =Commercial:0°C to 70°C
I =Industrial:-40°C to 85°C
Device
number
Access
time
Package:T=TSOP II
B=CSP BGA
Intelliwatt
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