AS7C25512PFS32A-133TQC [ALSC]
2.5V 512K x 32/36 pipelined burst synchronous SRAM; 2.5V 512K X 32/36流水线突发同步SRAM
| 型号： | AS7C25512PFS32A-133TQC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 2.5V 512K x 32/36 pipelined burst synchronous SRAM |
| 文件： | 总19页 (文件大小：523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2004
AS7C25512PFS32A
AS7C25512PFS36A
®
2.5V 512K × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 524,288 words × 32 or 36 bits
• Fast clock speeds to 166 MHz
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Fast clock to data access: 3.5/3.8 ns
• Fast OE access time: 3.5/3.8 ns
• Fully synchronous register-to-register operation
• Single-cycle deselect
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CE
Burst logic
CLR
512K × 32/36
Memory
array
19
17
19
19
D
CE
CLK
Q
A[18:0]
Address
register
36/32
36/32
GWE
BWE
BWd
D
Q
DQd
Byte write
registers
CLK
D
Q
DQc
Byte write
registers
BWc
BWb
CLK
D
Q
DQb
Byte write
registers
CLK
D
Q
DQa
Byte write
registers
4
BWa
CLK
CE0
CE1
OE
Output
registers
CLK
D
Q
Q
CE2
Input
registers
CLK
Enable
register
CE
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
36/32
DQ[a:d]
OE
Selection guide
-166
6
-133
7.5
133
3.8
270
75
Units
ns
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
166
3.5
290
85
MHz
ns
mA
mA
mA
Maximum CMOS standby current (DC)
40
40
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C25512PFS32A
AS7C25512PFS36A
®
16 Mb 2.5V Synchronous SRAM products list1,2
Org
Part Number
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
Speed
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
AS7C251MPFS18A
AS7C25512PFS32A
AS7C25512PFS36A
AS7C251MPFD18A
AS7C25512PFD32A
AS7C25512PFD36A
AS7C251MFT18A
AS7C25512FT32A
AS7C25512FT36A
AS7C251MNTD18A
AS7C25512NTD32A
AS7C25512NTD36A
AS7C251MNTF18A
AS7C25512NTF32A
AS7C25512NTF36A
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
1 Core Power Supply: VDD = 2.5V + 0.125V
2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V
PL-SCD
PL-DCD
FT
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
1
TM
NTD -PL
:
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
Flow-through Burst Synchronous SRAM with NTD
1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
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AS7C25512PFS32A
AS7C25512PFS36A
®
Pin assignment
100-pin TQFP - top view
1
2
3
4
5
6
7
8
9
NC/DQPc
DQc0
DQc1
VDDQ
VSSQ
DQPb/NC
DQb7
DQb6
VDDQ
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
10
11
12
VDDQ
DQc6
DQc7
NC
VDD
NC
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
TQFP 14 x 20mm
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
27
28
29
30
DQd6
DQd7
DQa1
DQa0
DQPa/NC
NC/DQPd
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.
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AS7C25512PFS32A
AS7C25512PFS36A
®
Functional description
The AS7C25512PFS32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device
organized as 524,288 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology.
Fast cycle times of 6/7.5 ns with clock access times (tCD) of 3.5/3.8 ns enable 166 MHz and 133 MHz bus frequencies. Three chip enable
(CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the
processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address
strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved
count sequence. With LBO driven low, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE
and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented
internally to the next burst address if BWn and ADV are sampled low. This device operates in single-cycle deselect feature during read
cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C25512PFS32A/36A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP package.
TQFP capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
Test conditions
VIN = 0V
Min
Max
Unit
pF
*
CIN
-
-
5
7
*
CI/O
VOUT = 0V
pF
* Guaranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
θJA
Typical
40
Units
°C/W
°C/W
1–layer
4–layer
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
θJA
22
Thermal resistance
(junction to top of case)1
θJC
8
°C/W
1 This parameter is sampled
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AS7C25512PFS32A
AS7C25512PFS36A
®
Signal descriptions
Pin
CLK
A,A0,A1
I/O Properties Description
I
I
CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
SYNC
SYNC
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
DQ[a,b,c,d] I/O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE0
I
I
SYNC
SYNC
Synchronous chip enables, active high, and active low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and
BW[a:d] control write enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is
low. If any of BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If
all BW[a:d] are inactive, the cycle is a read cycle.
BW[a,b,c,d]
I
SYNC
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read
mode.
OE
I
I
ASYNC
STATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
LBO
ZZ
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
NC
-
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
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AS7C25512PFS32A
AS7C25512PFS36A
®
Write enable truth table (per byte)
Function
GWE BWE BWa BWb BWc BWd
L
H
H
H
H
H
X
L
L
L
H
L
X
L
X
L
X
L
X
L
Write All Bytes
Write Byte a
L
H
H
X
H
H
L
H
L
Write Byte c and d
H
X
H
X
H
X
H
Read
Key: X = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal.
Asynchronous Truth Table
Operation
Snooze mode
ZZ
H
L
OE
X
I/O Status
High-Z
L
Dout
Read
L
H
High-Z
Write
L
X
Din, High-Z
High-Z
Deselected
L
X
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Interleaved burst address (LBO = 1)
Linear burst address (LBO = 0)
A1 A0
0 0
A1 A0
0 1
A1 A0
1 0
A1 A0
1 1
A1 A0
0 0
A1 A0
0 1
A1 A0
1 0
A1 A0
1 1
Starting Address
First Increment
Second Increment
Third Increment
Starting Address
First Increment
Second Increment
Third Increment
0 1
0 0
1 1
1 0
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
1 1
1 0
0 1
1 0
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AS7C25512PFS32A
AS7C25512PFS36A
®
Synchronous truth table[4]
[2]
CE01
H
L
CE1
X
L
CE2
X
X
X
H
H
L
ADSP ADSC ADV WRITE
OE
X
X
X
X
X
L
Address accessed
NA
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
NA
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
L
H
L
Next
Hi−Z
Q
H
H
L
Current
Current
Next
H
L
Hi−Z
Q
L
H
L
Next
Hi−Z
Q
H
H
X
L
Current
Current
External
Next
H
X
X
X
X
X
Hi−Z
3
D
X
H
X
H
X
X
X
X
H
H
H
H
L
D
D
D
D
L
L
Next
H
H
L
Current
Current
L
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all
BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
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AS7C25512PFS32A
AS7C25512PFS36A
®
Absolute maximum ratings
Parameter
Symbol
, V
Min
–0.3
–0.3
–0.3
–
Max
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
V
+3.6
DD
DDQ
V
V
+ 0.3
DD
V
IN
IN
V
V
+ 0.3
V
DDQ
P
1.8
W
d
Short circuit output current
Storage temperature
I
–
20
mA
OUT
o
T
–65
–65
+150
+135
C
stg
o
Temperature under bias
T
C
bias
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to abso-
lute maximum rating conditions may affect reliability.
Recommended operating conditions
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
Min
2.375
2.375
0
Nominal
Max
2.625
2.625
0
Unit
V
V
2.5
2.5
0
DD
V
V
DDQ
Vss
V
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AS7C25512PFS32A
AS7C25512PFS36A
®
DC electrical characteristics
Parameter
Input leakage current†
Output leakage current
Sym
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
µA
V
|ILI|
2
2
|ILO
|
-2
1.7*
1.7*
-0.3**
-0.3**
1.7
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
VIL
V
DDQ+0.3
V
Address and control pins
I/O pins
0.7
0.7
–
V
V
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
V
–
0.7
V
† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
*
V
max < VDD +1.5V for pulse width less than 0.2 X t
CYC
IH
**
V
min = -1.5 for pulse width less than 0.2 X t
CYC
IL
IDD operating conditions and maximum limits
Parameter
Sym
Conditions
-166
-133
Unit
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
,
Operating power supply current1
ICC
290
270
mA
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or >
V
– 0.2V, Deselected,
DD
ISB
85
75
f = fMax, ZZ < VIL
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Standby power supply current
mA
ISB1
ISB2
40
40
40
40
Deselected, f = f , ZZ
≥
V
– 0.2V,
Max
DD
all VIN ≤ VIL or ≥ VIH
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
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AS7C25512PFS32A
AS7C25512PFS36A
®
Timing characteristics over operating range
–166
Max
–133
1
Parameter
Clock frequency
Sym
Min
–
Min
–
Max
133
–
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
f
166
–
Max
Cycle time
t
6
7.5
–
CYC
Clock access time
t
–
3.5
3.5
–
3.8
3.8
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
OE
t
0
0
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
OH
t
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
-
3.8
3.8
–
t
–
-
HZC
t
0
0
OHOE
t
2.4
2.3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
5
5
CH
Clock low pulse width
t
t
t
–
–
CL
AS
DS
Address setup to clock high
Data setup to clock high
–
–
6
–
–
6
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 16.
t
–
–
6,7
6,8
6
WS
t
–
–
CSS
t
–
–
AH
DH
WH
t
–
–
6
t
–
–
6,7
6,8
6
t
–
–
CSH
t
–
–
ADVS
t
–
–
6
ADSPS
ADSCS
t
–
–
6
t
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
6
t
–
–
6
Snooze Mode Electrical Characteristics
Description
Conditions
ZZ > V
Symbol
Min
Max
Units
mA
Current during Snooze Mode
ZZ active to input ignored
I
40
IH
SB2
PDS
PUS
t
t
2
2
cycle
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
t
2
ZZI
t
0
RZZI
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Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
LOAD NEW ADDRESS
A3
tAH
tAS
A1
A2
Address
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
ADV inserts wait states
t
OE
tCD
tHZC
tHZOE
tOH
tLZOE
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
Q(A1)
Dout
Read Suspend Read
Burst
Read
Burst
Read
Suspend
Read
2Ý10
Burst
Read
Read
Q(A3)
Burst
Read
3Ý01
Burst
Read
3Ý10
Burst
Read
3Ý11
) Q(A )
Q(A1)
Read
Q(A2)
DSEL
Q(A1)
2Ý01
2Ý10
2Ý11
Q(A
) Q(A
) Q(A
) Q(A
)
Q(A
) Q(A
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
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Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
A3
tAS
tAH
A1
A2
Address
tWS
tWH
BWE
BW[a:d]
tCSS
tCSH
CE0, CE2
CE1
ADV SUSPENDS BURST
tADVH
tADVS
ADV
OE
tDS
tDH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Din
Read
Q(A1)
ADV
Burst
Write
Sus-
pend
Write
D(A1)
Suspend
Write
ADV
Burst
Write
Read
Q(A2)
ADV
Burst
Write
ADV
Burst
Write
Burst
Write
Suspend
Write
Write
3
D(A )
2
D(A )
3Ý01
2Ý01
D(A
)
D(A
)
2Ý01
D(A
)
3Ý10
2Ý10
2Ý11
D(A
)
D(A
)
D(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tAH
tAS
A2
A3
A1
Address
tWH
tWS
GWE
CE0, CE2
CE1
tADVH
tADVS
ADV
OE
tDH
tDS
Din
D(A2)
tOE
tCD
tLZC
tOH
tHZOE
tLZOE
Dout
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
DSEL
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Suspend
Write
Read
Q(A3)
ADV
Burst
Read
ADV
Burst
Read
ADV
Burst
Read
2
D(A )
3Ý01
3Ý10
3Ý11
Q(A )
Q(A
)
Q(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCYC
tCH
tCL
CLK
tADSCS
tADSCH
ADSC
tAS
tAH
A5
A9
A7
A8
A1
A4
A6
A3
A2
ADDRESS
tWS
tWH
GWE
CE0,CE2
CE1
tCSS
tCSH
ADV
OE
tOE
tLZOE
tOH
tHZOE
tLZOE
Q(A2)
Q(A1)
Q(A3)
Q(A8)
Q(A4)
Q(A9)
Dout
Din
tDH
tDS
D(A5)
D(A6)
D(A7)
READ
Q(A9)
WRITE
D(A7)
READ READ READ
Q(A1) Q(A2) Q(A3)
WRITE
D(A6)
READ
Q(A8)
READ
Q(A4)
WRITE
D(A5)
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Timing waveform of power down cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPS
ADSP
ADSC
A2
A1
ADDRESS
GWE
tWH
tWS
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
tLZOE
Din
D(A2)
tHZOE
D(A2(Ý01))
tHZC
Dout
Q(A1)
tPUS
tPDS
ZZ Recovery Cycle
Normal Operation Mode
ZZ
ZZ Setup Cycle
tZZI
tRZZI
ISB2
Isupply
Sleep
State
READ
Q(A2)
CON-
TINUE
SUSPEND
WRITE
D(A2)
SUSPEND
READ
Q(A1)
READ
Q(A1)
WRITE
Ý01)
D(A2
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AC test conditions
• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 2.5V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.25V.
+2.5V
319Ω/1667Ω
Z0 = 50Ω
50
Ω
DOUT
+2.5V
VL = VDDQ/2
DOUT
5 pF*
90%
10%
90%
10%
353Ω/1538Ω
30 pF*
GND *including scope
and jig capacitance
GND
Figure C: Output load(B)
Figure A: Input waveform
Figure B: Output load (A)
Notes
1
2
3
4
5
6
For test conditions, see “AC test conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
t
t
HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
CH is measured as high if above VIH, and tCL is measured as low if below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
,
BWE, and BW[a:d].
CE1, and CE2
Chip select refers to CE0
,
.
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®
Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Hd
D
Min
Max
A1
A2
b
0.05
0.15
1.35
1.45
b
e
0.22
0.38
c
0.09
0.20
D
13.90
19.90
14.10
20.10
E
e
0.65 nominal
Hd
He
L
15.85
21.80
0.45
16.15
22.20
0.75
He
E
L1
α
1.00 nominal
0°
7°
Dimensions in millimeters
c
α
L1
L
A1 A2
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Ordering information
Package & Width
-166
-133
AS7C25512PFS32A-166TQC
AS7C25512PFS32A-166TQI
AS7C25512PFS36A-166TQC
AS7C25512PFS36A-166TQI
AS7C25512PFS32A-133TQC
TQFP x32
AS7C25512PFS32A-133TQI
AS7C25512PFS36A-133TQC
AS7C25512PFS36A-133TQI
TQFP x36
Note:
Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C25512PFS32A-166TQCN)
Part numbering guide
AS7C
25
512
PF
S
32/36
A
–XXX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
11
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 25 = 2.5V
3. Organization: 512 = 512K
4. Pipelined mode
5. Deselect: S = single cycle deselect
6. Organization: 32 = x 32; 36 = x 36
7. Production version: A = first production version
8. Clock speed (MHz)
9. Package type: TQ = TQFP
10. Operating temperature: C = commercial (
11. N = Lead Free Part
0° C to 70° C); I = industrial (-40° C to 85° C)
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AS7C25512PFS36A
®
®
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C25512PFS32A
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
AS7C25512PFS36A
Document Version: v. 2.2
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alli-
ance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products
at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/
or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under develop-
ment, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential cus-
tomers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability
arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
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