AS7C256B [ALSC]
5V 32K X 8 CMOS SRAM (Common I/O); 5V 32K ×8 CMOS SRAM （通用I / O）
| 型号： | AS7C256B |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 5V 32K X 8 CMOS SRAM (Common I/O) |
| 文件： | 总8页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2006
Advance Information
AS7C256B
®
5V 32K X 8 CMOS SRAM (Common I/O)
Features
• Industrial (-40o to 85oC) temperature
• Organization: 32,768 words × 8 bits
• High speed
• 28-pin JEDEC standard packages
- 300 mil SOJ
- 8 × 13.4 mm TSOP
- 300 mil PDIP
- 12 ns address access time
• ESD protection ≥ 2000 volts
- 6 ns output enable access time
• Low power consumption via chip deselect
• One chip select plus one Output Enable pin
• Bidirectional data inputs and outputs
• TTL-compatible
Logic block diagram
Pin arrangement
28-pin DIP, SOJ (300 mil)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
VCC
WE
A13
A8
A9
A11
OE
VCC
GND
Input buffer
A10
CE
9
A0
A1
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
I/O7
I/O0
A2
32,768 X 8
17
16
15
A3
Array
A4
(262,144)
A5
A6
A7
28-pin TSOP 1 (8×13.4mm)
OE
A11
A9
1
A10
CE
(22)
(21) 28
(20) 27
(19) 26
(18) 25
(17) 24
(16) 23
(15) 22
(14) 21
(13) 20
(12) 19
(11) 18
(10) 17
(9) 16
(8) 15
2
(23)
(24)
(25)
(26)
(27)
(28)
(1)
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A8
4
WE
OE
CE
A13
WE
VCC
A14
A12
A7
5
Address decoder
6
Control
circuit
7
AS7C256B
8
9
(2)
10
11
12
13
14
(3)
(4)
A6
A
8
A
9
A A A A A
10 11 12 13 14
(5)
A5
(6)
A4
A1
A2
(7)
A3
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
12/5/06; V.1.0
Alliance Memory
P. 1 of 8
Copyright © Alliance Memory. All rights reserved.
AS7C256B
®
Functional description
The AS7C256B is a 5V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as
32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM
,
PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation
without sacrificing performance or operating margins.
The device enters standby mode when CE is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output
enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory
expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C256B is packaged in
high volume industry standard packages.
Absolute maximum ratings
Parameter
Voltage on VCC relative to GND
Voltage on any pin relative to GND
Power dissipation
Symbol
Vt1
Min
–0.5
–0.5
–
Max
+7.0
Unit
V
Vt2
VCC + 0.5
1.25
V
PD
W
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Note:
Tstg
–55
–55
–
+125
+125
50
oC
oC
mA
Tbias
IOUT
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Data
High Z
High Z
DOUT
DIN
Mode
CE
H
L
WE
X
OE
X
Standby (ISB, ISB1
)
H
H
Output disable (ICC
Read (ICC
Write (ICC
)
L
H
L
)
L
L
X
)
Notes:
H = V , L = V , x = Don’t care.
IH
IL
V
= 0.2V, V = V - 0.2V.
LC
HC CC
Other inputs ≥ V or V
.
HC
LC
12/5/06; V.1.0
Alliance Memory
P. 2 of 8
AS7C256B
®
Recommended operating conditions
Parameter
Symbol
VCC
Min
4.5
Typical
Max
Unit
V
Supply voltage
Input voltage
5.0
–
5.5
VCC+0.5
0.8
VIH
2.2
-0.5(1)
V
(1)
VIL
–
V
Ambient operating temperature (Industrial)
TA
–40
–
85
oC
Note:
1
V
min = –1.5V for pulse width less than 10ns, once per cycle.
IL
DC operating characteristics (over the operating range)1
AS7C256B-12
Parameter
Input leakage current
Symbol
Test conditions
Min
Max Unit
VCC = Max,
V
|ILI|
–
5
5
µA
µA
in = GND to VCC
VCC = Max, CS = VIH
,
Output leakage current
|ILO
ICC
ISB
|
–
–
–
V
OUT = GND to VCC
VCC = Max, CE ≤ VIL
Operating power supply current
160
50
mA
mA
f = fMax, IOUT = 0mA
VCC = Max, CE > VIH
f = fMax, IOUT = 0mA
Standby power supply current
Output voltage
VCC = Max, CE > VCC–0.2V
ISB1
–
15
mA
V
V
IN < GND + 0.2V or
IN > VCC–0.2V, f = 0(2)
VOL
VOH
IOL = 8 mA, VCC = Min
IOH = –4 mA, VCC = Min
–
0.4
–
V
V
2.4
Notes:
All values are maximum guaranteed values.
f
= 1/t , only address inputs cycling at f , f = 0 means that no inputs are cycling.
RC Max
Max
Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2
Parameter
Symbol
Signals
A, CE WE
I/O
Test conditions
Max
Unit
pF
Input capacitance
CIN
Vin = 3dV
7
7
,
, OE
I/O capacitance
CI/O
Vout = 3dV
pF
Note:
This parameter is guaranteed by device characterization, but is not production tested.
12/5/06; V.1.0
Alliance Memory
P. 3 of 8
AS7C256B
®
Read cycle (over the operating range)3,9
AS7C256B-12
Parameter
Read cycle time
Symbol
Min
12
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
tRC
Address access time
tAA
12
12
6
3
3
tACE
tOE
–
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE LOW to output in low Z
CE HIGH to output in high Z
OE LOW to output in low Z
OE HIGH to output in high Z
Power up time
–
tOH
3
–
5
tCLZ
tCHZ
tOLZ
tOHZ
tPU
4
–
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
0
6
0
–
0
6
0
–
Power down time
tPD
–
12
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)3,6,7,9
t
RC
Address
tAA
t
OH
D
Data valid
out
Read waveform 2 (CE controlled)3,6,8,9
t
RC
CE
OE
t
OE
t
t
t
OLZ
OHZ
CHZ
t
ACE
D
out
Data valid
t
CLZ
t
PD
I
I
CC
t
PU
Supply
current
SB
50%
50%
12/5/06; V.1.0
Alliance Memory
P. 4 of 8
AS7C256B
®
Write cycle (over the operating range)11
AS7C256B-12
Parameter
Write cycle time
Symbol
Min
12
9
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
tWC
Chip enable to write end
Address setup to write end
Address setup time
tCW
tAW
tAS
–
9
–
0
–
Write pulse width
tWP
tWR
tAH
tDW
tDH
tWZ
tOW
8
–
Write recovery time
0
–
Address hold from end of write
Data valid to write end
Data hold time
0
–
6
–
0
–
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
Shaded areas contain advance information.
0
6
4
–
Write waveform 1 (WE controlled)10,11
t
WC
t
AH
t
AW
t
WR
Address
WE
t
WP
t
AS
t
t
DH
DW
Data valid
D
in
t
t
WZ
OW
D
out
Write waveform 2 (CE controlled)10,11
t
WC
t
t
AH
AW
t
WR
Address
CE
t
t
CW
AS
t
WP
WE
t
t
t
DH
WZ
DW
D
Data valid
in
D
out
12/5/06; V.1.0
Alliance Memory
P. 5 of 8
AS7C256B
®
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to
- Input rise and fall times: 3 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Thevenin equivalent
168
V
CC. See Figure A.
Ω
D
+1.72V (5V)
out
V
CC
480Ω
D
out
V
CC
90%
10%
90%
10%
255
Ω
C(13)
3 ns
Figure A: Input pulse
GND
GND
Figure B: Output load
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±200mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
12/5/06; V.1.0
Alliance Memory
P. 6 of 8
AS7C256B
®
Package diagrams
28-pin SOJ
Min
Max
in mils
D
e
B
-
0.140
A
A1
A2
B
b
c
0.025
0.095
-
A
A1
0.105
E1 E2
0.028 TYP
Seating
Plane
b
0.018 TYP
0.010 TYP
Pin 1
c
-
0.730
0.285
0.305
0.347
D
E
E1
E2
e
A2
0.245
0.295
0.327
E2
0.050 BSC
28-pin TSOP
8×13.4 mm
e
b
Min
Max
c
–
1.20
A
A2
A
A1
L
0.10
0.95
0.15
0.20
1.05
0.25
A1
A2
b
c
D
e
E
pin 1(22)
pin 8(21)
pin 5(8)
0.10
0.20
D
Hd
11.60
11.80
α
0.55 nominal
8.0 nominal
13.30
13.50
pin 1(7)
Hd
0.50
0°
0.70
5°
L
α
28-pin
E
28-pin PDIP
Min
Max
in mils
-
0.180
A
A1
B
b
c
D
E
E1
e
A
D
0.010
0.040
0.014
0.008
-
-
B
S
0.065
0.022
0.014
1.400
0.320
0.298
E
E1
α
c
L
A1
eA
e
b
0.295
0.278
Seating
Plane
Pin 1
0.100 BSC
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
0.330
0.120
0°
0.380
0.140
15°
eA
L
a
-
0.055
S
12/5/06; V.1.0
Alliance Memory
P. 7 of 8
AS7C256B
®
Ordering information
Package
Volt/Temp
12 ns
Plastic DIP, 300 mil
Plastic SOJ, 300 mil
TSOP 8x13.4 mm
5V industrial
5V industrial
5V industrial
AS7C256B-12PIN
AS7C256B-12JIN
AS7C256B-12TIN
Part numbering system
AS7C
256B
–XX
X
I
X
Package:
P=DIP 300 mil
J=SOJ 300 mil
T=TSOP 8x13.4 mm
Temperature range:
I = -40C to 85C
SRAM prefix Device number Access time
N=Lead Free Part
®
Alliance Memory, Inc.
1116 South Amphlett
San Mateo, CA 94402
Tel: 650-525-3737
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS7C256B
Document Version: v.1.0
Fax: 650-525-0449
www.alliancememory.com
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time,
without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product
data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or
warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described
herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness
for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions
of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The
purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual
property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting
systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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