AS7C31025A-15 [ALSC]
SRAM;
| 型号： | AS7C31025A-15 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | SRAM 静态存储器 |
| 文件： | 总8页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2001
Advance Information
AS7C1025A
AS7C31025A
®
5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout)
• Latest 6T 0.25u CMOS technology
• 2.0V data retention
Features
• AS7C1025A (5V version)
• AS7C31025A (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Low power consumption: ACTIVE
- 660 mW (AS7C1025A) / max @ 10 ns (5V)
- 324 mW (AS7C31025A) / max @ 10 ns (3.3V)
• Low power consumption: STANDBY
- 55 mW (AS7C1025A) / max CMOS (5V)
- 36 mW (AS7C31025A) / max CMOS (3.3V)
• Easy memory expansion with CE
• Center power and ground
, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin, TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
32-pin TSOP II
A0
A1
A2
1
2
3
32
31
30
29
A16
A15
A14
A13
OE
I/O7
I/O6
GND
Logic block diagram
A3
4
28
27
26
25
24
23
22
21
CE
I/O0
I/O1
5
6
7
8
9
10
11
12
V
CC
V
CC
GND
I/O2
I/O3
WE
V
CC
GND
I/O5
I/O4
A12
A11
A10
A9
Input buffer
20
19
18
17
13
14
15
16
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O7
I/O0
A8
512
×256×8
Array
(1,048,576)
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A16
A0
1
32
31
30
A15
A14
A13
OE
I/O7
A1
A2
A3
CE
I/O0
I/O1
2
3
4
5
6
7
29
28
27
26
25
24
23
22
21
20
19
WE
Control
circuit
Column decoder
I/O6
GND
OE
CE
V
8
CC
V
GND
I/O2
I/O3
WE
A4
A5
A6
A7
9
10
11
12
13
14
15
16
CC
I/O5
I/O4
A12
A11
A10
A9
18
17
A8
Selection guide
AS7C1025A-10
AS7C31025A-10 AS7C31025A-12
AS7C1025A-12
AS7C1025A-15
AS7C31025A-15
AS7C1025A-20
AS7C31025A-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access
time
3
3
4
5
ns
Maximum
operating
current
AS7C1025A
AS7C31025A
AS7C1025A
AS7C31025A
120
90
110
80
100
80
100
80
mA
mA
mA
mA
Maximum
CMOS standby
current
10
10
10
15
10
10
10
15
2/6/01; V.0.9
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C1025A
AS7C31025A
®
Functional description
The AS7C1025A and AS7C31025A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high the devices enter standby mode. The standard AS7C1025A is guaranteed not to exceed 55 mW power consumption in
standby mode. Both devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O7 is written on the rising
edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025A) or 3.3V supply (AS7C31025A). The
AS7C1025A and AS7C31025A are packaged in common industry standard packages.
Absolute maximum ratings
Parameter
Device
Symbol
Vt1
Min
–0.50
–0.50
–0.50
–
Max
+7.0
Unit
V
AS7C1025A
AS7C31025A
Voltage on VCC relative to GND
Vt1
+5.0
V
Voltage on any pin relative to GND
Power dissipation
Vt2
VCC + 0.5
1.0
V
PD
W
oC
oC
mA
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Tstg
–65
–55
–
+150
+125
20
Tbias
IOUT
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
WE
X
OE
X
Data
High Z
High Z
DOUT
DIN
Mode
Standby (ISB, ISB1
)
H
H
L
Output disable (ICC)
Read (ICC
Write (ICC)
L
H
)
L
L
X
Key: X = Don’t Care, L = Low, H = High
2/6/01; V.0.9
Alliance Semiconductor
P. 2 of 8
AS7C1025A
AS7C31025A
®
Recommended operating conditions
Parameter
Device
Symbol
VCC
Min
4.5
3.0
2.2
2.0
–0.5
0
Nominal
Max
5.5
Unit
V
AS7C1025A
5.0
3.3
–
Supply voltage
Input voltage
AS7C31025A
AS7C1025A
AS7C31025A
Both
VCC
3.6
V
VIH
VCC + 0.5
VCC + 0.5
0.8
V
VIH
–
V
†
VIL
–
V
commercial
industrial
TA
TA
–
70
oC
oC
Ambient operating temperature
–40
–
85
†
V
min. = –3.0V for pulse width less than t /2.
RC
IL
DC operating characteristics (over the operating range)1
-10
-12
-15
-20
Parameter Sym
Test conditions
Device
Min Max Min Max Min Max Min Max Unit
Input
leakage
current
| ILI |
V
CC = Max, VIN = GND to VCC
Both
–
–
1
1
–
–
1
1
–
–
1
1
–
–
1
1
µA
µA
Output
leakage
current
V
CC = Max, CE = VIH, Vout = GND
to VCC
| ILO
|
Both
Operating
power
supply
AS7C1025A
–
–
120
90
–
–
110
80
–
–
100
80
–
–
100
80
ICC
CE = VIL, f = fMax, IOUT = 0 mA
mA
AS7C31025A
current
AS7C1025A
AS7C31025A
AS7C1025A
AS7C31025A
AS7C1025A
AS7C31025A
AS7C1025A
–
–
30
30
10
10
.04
–
–
25
25
10
10
0.4
–
–
–
20
20
10
10
0.4
–
–
–
20
20
15
15
0.4
–
Standby
power
ISB
CE = VIH, f = fMax, fOUT = 0
mA
mA
supply
–
–
–
–
CE ≥ VCC–0.2V, VIN ≤ 0.2V or VIN
≥ VCC –0.2V, f = 0, fOUT = 0
current1
ISB1
–
–
–
–
VOL
IOL = 8 mA, VCC = Min
IOH = –4 mA, VCC = Min
VCC = 2.0V
–
–
–
–
V
V
Output
voltage
VOH
2.4
–
2.4
–
2.4
–
2.4
1
1
1
1
5
mA
Data
retention
current
ICCDR
CE ≥ VCC – 0.2V
AS7C31025A
–
–
1
–
1
–
5
mA
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
Capacitance (f = 1 MHz, Ta = 25 oC, VCC = NOMINAL)2
Parameter
Symbol
Signals
A, CE WE
I/O
Test conditions
VIN = 0V
Max
Unit
Input capacitance
CIN
,
,
OE
5
7
pF
pF
I/O capacitance
CI/O
VIN = VOUT = 0V
2/6/01; V.0.9
Alliance Semiconductor
P. 3 of 8
AS7C1025A
AS7C31025A
®
Read cycle (over the operating range)3,9
-10
-12
-15
-20
Parameter
Read cycle time
Symbol Min Max Min Max Min Max Min Max
Unit
Notes
tRC
tAA
tACE
tOE
10
–
–
10
10
3
12
–
–
12
12
3
15
–
–
15
15
4
20
–
–
20
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
3
3
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE Low to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
–
–
–
–
–
–
–
–
tOH
tCLZ
tCHZ
tOLZ
tOHZ
tPU
2
0
–
–
3
0
–
–
3
0
–
–
3
0
–
–
5
–
–
–
–
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
3
3
4
5
0
–
–
0
–
–
0
–
–
0
–
–
3
3
4
5
0
–
–
0
–
–
0
–
–
0
–
–
Power down time
tPD
10
12
15
20
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
t
RC
Address
t
t
AA
OH
D
Data valid
OUT
Read waveform 2 (CE and OE controlled)3,6,8,9
t
RC1
CE
t
OE
OE
t
t
OHZ
OLZ
t
CHZ
t
ACE
D
OUT
Data valid
t
CLZ
t
I
I
PD
CC
SB
t
PU
Supply
current
50%
50%
2/6/01; V.0.9
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P. 4 of 8
AS7C1025A
AS7C31025A
®
Write cycle (over the operating range)11
-10
-12
-15
-20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max
Unit
Notes
tWC
tCW
tAW
tAS
10
8
12
10
9
–
–
–
–
–
–
–
–
6
–
15
12
10
0
–
–
–
–
–
–
–
–
6
–
20
12
12
0
–
–
–
–
–
–
–
–
8
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable (CE) to write end
Address setup to write end
Address setup time
8
0
0
Write pulse width
tWP
tAH
tDW
tDH
tWZ
tOW
7
8
9
12
0
Address hold from end of write
Data valid to write end
Data hold time
0
0
0
5
6
8
10
0
0
0
0
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
6
–
–
–
1
1
1
2
Write waveform 1 (WE controlled)10,11
t
WC
t
t
AW
AH
DH
Address
WE
t
WP
t
AS
t
t
DW
D
Data valid
IN
t
t
WZ
OW
D
OUT
Write waveform 2 (CE controlled)10,11
t
WC
t
t
AH
AW
Address
t
t
CW
AS
CE
t
WP
WE
t
t
t
DH
WZ
DW
D
Data valid
IN
D
OUT
2/6/01; V.0.9
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P. 5 of 8
AS7C1025A
AS7C31025A
®
Data retention characteristics (over the operating range)
Parameter
Symbol
Test conditions
Min
2.0
–
Max
–
Unit
V
V
CC for data retention
VDR
VCC = 2.0V
Data retention current
ICCDR
tCDR
tR
500
–
µA
ns
CE ≥ VCC – 0.2V
Chip enable to data retention time
Operation recovery time
Input leakage current
0
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
tRC
–
–
ns
| ILI |
1
µA
Data retention waveform
Data retention mode
2.0V
V
V
V
≥
V
CC
CC
CC
DR
t
t
R
CDR
V
DR
V
V
IH
CE
IH
AC test conditions
– Output load: see Figure B or Figure C.
Thevenin equivalent:
168W
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
D
D
+1.728V (5V and 3.3V)
OUT
+5V
+3.3V
480W
320W
D
OUT
OUT
+3.0V
GND
90%
10%
90%
10%
255W
C(14)
GND
255W
C(14)
GND
2 ns
Figure A: Input pulse
Figure B: 5V Output load
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
t
and t
are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
CHZ
CLZ
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 NA.
13 C=30pF, except all high Z and low Z parameters, where C=5pF.
2/6/01; V.0.9
Alliance Semiconductor
P. 6 of 8
AS7C1025A
AS7C31025A
®
Package dimensions
32-pin TSOP II (mm)
32-pin TSOP II
Symbol
Min
–
Max
1.2
A
A1
b
N
N/2+1
0.05
0.3
0.15
0.52
0.21
21.08
10.29
11.96
E
E1
C
0.12
20.82
10.03
11.56
D
E1
E
1
N/2
D
e
1.27 BSC
Seating plane
A
L
0.40
0°
0.60
5°
ZD
ZD
α
0.95 REF.
A1
c
b
L
α
c
32-pin SOJ
300 mil
Symbol Min Max
32-pin SOJ
400 mil
Min
-
Max
0.145
-
A
A1
A2
B
-
0.145
-
0.025
0.025
32-pin SOJ
300 mil/400 mil
0.086 0.105 0.086 0.115
0.026 0.032 0.026 0.032
0.014 0.020 0.015 0.020
0.006 0.013 0.007 0.013
0.820 0.830 0.820 0.830
0.250 0.275 0.360 0.380
0.292 0.305 0.395 0.405
0.330 0.340 0.435 0.445
D
e
b
E1
c
E2
D
E
B
Pin 1
E1
E2
e
A
A1
c
Seating
Plane
b
0.050 BSC
0.050 BSC
A2
E
2/6/01; V.0.9
Alliance Semiconductor
P. 7 of 8
AS7C1025A
AS7C31025A
®
Ordering codes
Package \
Access time Voltage Temperature
10 ns
12 ns
15 ns
20 ns
Commercial
AS7C1025A-10TC
AS7C1025A-10TI
AS7C31025A-10TC
AS7C31025A-10TI
AS7C1025A-10TJC
AS7C1025A-10TJI
AS7C1025A-12TC
AS7C1025A-12TI
AS7C31025A-12TC
AS7C31025A-12TI
AS7C1025A-12TJC
AS7C1025A-12TJI
AS7C1025A-15TC
AS7C1025A-15TI
AS7C31025A-15TC
AS7C31025A-15TI
AS7C1025A-15TJC
AS7C1025A-15TJI
AS7C1025A-20TC
AS7C1025A-20TI
AS7C31025A-20TC
AS7C31025A-20TI
AS7C1025A-20TJC
AS7C1025A-20TJI
AS7C31025A-20TJC
AS7C31025A-20TJI
AS7C1025A-20JC
AS7C1025A-20JI
AS7C31025A-20JC
AS7C31025A-20JI
5V
Industrial
TSOP II
Commercial
3.3V
Industrial
Commercial
5V
Industrial
300-mil SOJ
Commercial
3.3V
AS7C31025A-10TJC AS7C31025A-12TJC AS7C31025A-15TJC
Industrial
AS7C31025A-10TJI
AS7C1025A-10JC
AS7C1025A-10JI
AS7C31025A-10JC
AS7C31025A-10JI
AS7C31025A-12TJI
AS7C1025A-12JC
AS7C1025A-12JI
AS7C31025A-12JC
AS7C31025A-12JI
AS7C31025A-15TJI
AS7C1025A-15JC
AS7C1025A-15JI
AS7C31025A-15JC
AS7C31025A-15JI
Commercial
5V
Industrial
400-mil SOJ
Commercial
3.3V
Industrial
Part numbering system
AS7C
X
1025
–XX
X
X
Package:
T = TSOP II
J = SOJ
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
SRAM Blank=5V CMOS Device Access
prefix 3=3.3V CMOS number time
2/6/01; V.0.9
Alliance Semiconductor
P. 8 of 8
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and
product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no
responsibility for any errors that may appear in this document. The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to
change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this
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against all claims arising from such use.
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