AS7C31025B-12TJI [ALSC]
3.3V 128K X 8 CMOS SRAM (Center power and ground); 3.3V 128K ×8 CMOS SRAM （中心电源和地）
| 型号： | AS7C31025B-12TJI |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 128K X 8 CMOS SRAM (Center power and ground) |
| 文件： | 总9页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2004
AS7C31025B
®
3.3V 128K X 8 CMOS SRAM (Center power and ground)
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
• Easy memory expansion with CE
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
, OE inputs
• Low power consumption: STANDBY
- 18 mW / max CMOS
• 6 T 0.18 u CMOS technology
Pin arrangement
Logic block diagram
V
CC
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
GND
Input buffer
A16
A0
1
32
31
30
A15
A14
A13
OE
I/O7
A1
A2
A3
CE
I/O0
I/O1
2
3
4
5
6
7
A0
A1
A2
A3
A4
A5
A6
A7
A8
29
28
27
26
25
24
23
22
21
20
19
I/O7
I/O0
512 x 256 x 8
Array
(1,048,576)
I/O6
GND
V
8
CC
V
GND
I/O2
I/O3
WE
A4
A5
A6
A7
9
10
11
12
13
14
15
16
CC
I/O5
I/O4
A12
A11
A10
WE
A9
A8
18
17
Control
circuit
Column decoder
OE
CE
Selection guide
-10
-12
12
6
-15
15
7
-20
20
8
Unit
ns
Maximum address access time
Maximum output enable access time
Maximum operating current
10
5
ns
70
5
65
5
60
5
55
5
mA
mA
Maximum CMOS standby current
3/24/04, v. 1.3
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
AS7C31025B
®
Functional description
The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8
bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packaged in common
industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
–0.50
–0.50
–
Max
Unit
V
Voltage on V relative to GND
V
V
+5.0
CC
t1
t2
D
Voltage on any pin relative to GND
Power dissipation
V
+ 0.5
V
CC
P
1.0
+150
+125
20
W
o
Storage temperature (plastic)
T
–65
–55
–
C
stg
bias
o
Ambient temperature with V applied
T
C
CC
DC current into outputs (low)
I
mA
OUT
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
WE
X
OE
X
Data
Mode
Standby (I , I
High Z
High Z
)
SB SB1
H
H
Output disable (I
)
CC
L
H
L
D
Read (I
)
OUT
CC
L
L
X
D
Write (I
)
IN
CC
Key: X = don’t care, L = low, H = high.
3/24/04, v. 1.3
Alliance Semiconductor
P. 2 of 9
AS7C31025B
®
Recommended operating conditions
Parameter
Symbol
Min
3.0
2.0
–0.5
0
Nominal
Max
Unit
V
Supply voltage
V
3.3
–
3.6
CC
V
V
+ 0.5
CC
V
IH
Input voltage
V
–
0.8
70
85
V
IL
o
T
–
C
A
Ambient operating temperature
o
T
–40
–
C
A
VIL = -1.0V for pulse width less than 5ns
V
V
+ 1.5V for pulse width less than 5ns
IH = CC
DC operating characteristics (over the operating range)1
-10
-12
-15
-20
Parameter
Sym
Test conditions
= Max, V = GND to V
CC
Min Max Min Max Min Max Min Max Unit
Input leakage
current
| ILI
|
V
–
–
1
1
–
–
1
1
–
–
1
1
–
–
1
1
µA
µA
CC
IN
V
= Max, CE = V ,
IH
Output leakage
current
CC
| ILO
|
V
= GND to V
out
CC
V
= Max
CC
Operating power
supply current
ICC
–
70
–
65
–
60
–
55
mA
CE ≤ V , f = f
,
IL
Max
I
= 0 mA
OUT
V
= Max
CC
ISB
–
–
30
5
–
–
25
5
–
–
20
5
–
–
20
5
mA
mA
CE ≥ V , f = f
IH
Max
Standby power
supply current1
V
= Max, CE ≥ V –0.2 V,
CC
≤ 0.2 V or V ≥ V –0.2 V,
CC
ISB1
V
IN
IN
CC
f = 0
VOL
VOH
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
I
= 8 mA, V = Min
CC
OL
Output voltage
I
= –4 mA, V = Min
2.4
2.4
2.4
2.4
OH
CC
o
Capacitance (f = 1 MHz, T = 25 C, V = NOMINAL)2
a
CC
Parameter
Input capacitance
I/O capacitance
Symbol
Signals
Test conditions
= 0 V
Max
Unit
C
A, CE
,
WE
,
OE
V
5
7
pF
pF
IN
IN
C
I/O
V
= V
= 0 V
OUT
I/O
IN
3/24/04, v. 1.3
Alliance Semiconductor
P. 3 of 9
AS7C31025B
®
Read cycle (over the operating range)3,9
-10
-12
-15
-20
Parameter
Read cycle time
Symbol Min Max Min Max Min Max Min Max Unit Notes
t
10
–
–
–
3
3
–
0
–
0
–
–
10
10
5
12
–
–
–
3
3
–
0
–
0
–
–
12
12
6
15
–
–
–
3
3
–
0
–
0
–
–
15
15
7
20
–
–
–
3
3
–
0
–
0
–
–
20
20
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address access time
t
3
3
AA
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE low to output in low Z
CE high to output in high Z
OE low to output in low Z
OE high to output in high Z
Power up time
t
ACE
t
OE
OH
t
–
–
–
–
5
t
–
–
–
–
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
CLZ
CHZ
t
3
3
4
5
t
–
–
–
–
OLZ
OHZ
t
5
6
7
8
t
t
–
–
–
–
PU
PD
Power down time
10
12
15
20
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
t
RC
Address
t
t
AA
OH
D
Data valid
OUT
Read waveform 2 (CE and OE controlled)3,6,8,9
t
RC1
CE
t
OE
OE
t
t
OHZ
OLZ
t
CHZ
t
ACE
D
OUT
Data valid
t
t
CLZ
t
I
PD
CC
PU
Supply
current
I
SB
50%
50%
3/24/04, v. 1.3
Alliance Semiconductor
P. 4 of 9
AS7C31025B
®
Write cycle (over the operating range)11
-10
-12
-15
-20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max Unit
Notes
t
t
t
10
8
8
0
7
0
0
5
0
–
1
–
–
–
–
–
–
–
–
–
5
–
12
9
9
0
8
0
0
6
0
–
1
–
–
–
–
–
–
–
–
–
6
–
15
10
10
0
–
–
–
–
–
–
–
–
–
7
–
20
12
12
0
–
–
–
–
–
–
–
–
–
8
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
Chip enable (CE) to write end
Address setup to write end
Address setup time
t
AS
WP
WR
Write pulse width
t
9
12
0
Write recovery time
t
0
Address hold from end of write
Data valid to write end
Data hold time
t
0
0
AH
t
8
10
0
DW
t
0
4, 5
4, 5
4, 5
DH
WZ
OW
Write enable to output in high Z
Output active from write end
t
–
–
t
1
1
Write waveform 1 (WE controlled)10,11
t
WC
t
t
WR
t
AW
AH
Address
WE
t
WP
t
AS
t
t
DW
DH
D
Data valid
IN
t
t
WZ
OW
D
OUT
Write waveform 2 (CE controlled)10,11
t
WC
t
t
AH
AW
t
WR
Address
t
t
CW
AS
CE
t
WP
WE
t
t
t
DH
WZ
DW
D
Data valid
IN
D
OUT
3/24/04, v. 1.3
Alliance Semiconductor
P. 5 of 9
AS7C31025B
®
AC test conditions
– Output load: see Figure B.
Thevenin equivalent:
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
168
Ω
D
+1.728 V
+3.3 V
OUT
320
Ω
D
OUT
+3.0 V
13
90%
10%
90%
10%
255
Ω
C
2 ns
Figure A: Input pulse
GND
Figure B: 3.3 V Output load
GND
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
t
CLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
3/24/04, v. 1.3
Alliance Semiconductor
P. 6 of 9
AS7C31025B
®
Package dimensions
32-pin SOJ
300 mil/400 mil
D
e
E1
A1
E2
B
Pin 1
A
c
Seating
plane
b
A2
E
32-pin SOJ
300 mil
32-pin SOJ
400 mil
Symbol Min
Max
0.128 0.145 0.132 0.146
0.025 0.025
Min
Max
A
A1
A2
B
-
-
0.095 0.105 0.105 0.115
0.026 0.032 0.026 0.032
0.016 0.020 0.015 0.020
0.007 0.010 0.007 0.013
0.820 0.830 0.820 0.830
0.255 0.275 0.354 0.378
0.295 0.305 0.395 0.405
0.330 0.340 0.435 0.445
b
c
D
E
E1
E2
e
0.050 BSC
0.050 BSC
3/24/04, v. 1.3
Alliance Semiconductor
P. 7 of 9
AS7C31025B
®
Ordering Codes
Package \
Access time
Temperature
Commercial
Industrial
10 ns
12 ns
15 ns
20 ns
AS7C31025B-10TJC
AS7C31025B-10TJI
AS7C31025B-10JC
AS7C31025B-10JI
AS7C31025B-12TJC
AS7C31025B-12TJI
AS7C31025B-12JC
AS7C31025B-12JI
AS7C31025B-15TJC AS7C31025B-20TJC
300-mil SOJ
AS7C31025B-15TJI
AS7C31025B-15JC
AS7C31025B-15JI
AS7C31025B-20TJI
AS7C31025B-20JC
AS7C31025B-0JI
Commercial
Industrial
400-mil SOJ
Note:
Add suffix ‘N’ to the above part number for lead free parts (Ex. AS7C31025B-10TJCN)
Part numbering system
AS7C
X
1025B
–XX
X
X
X
Voltage:
3 = 3.3 V
CMOS
Package:
Temperature range
SRAM
prefix
Device Access
number time
TJ = SOJ 300 mil C = commercial, 0° C to 70° C
J = SOJ 400 mil I = industrial, -40° C to 85° C
N=Lead Free Part
3/24/04, v. 1.3
Alliance Semiconductor
P. 8 of 9
AS7C31025B
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C31025B
Document Version: v. 1.3
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The
information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application
or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including
liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express
agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according
to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask
works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify
Alliance against all claims arising from such use.
相关型号：
©2020 ICPDF网 联系我们和版权申明