AS7C3128PFS36A-3.5TQC [ALSC]
Standard SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100;
| 型号： | AS7C3128PFS36A-3.5TQC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 静态存储器 |
| 文件： | 总9页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-performance
4Mb synchronous
CMOS SRAM
AS7C3128PFS32/ 36A
®
128K × 32/ 36 synchronous SRAM
Advance information
Features
• Byte write enables
• Organization: 131,072 words × 32 or 36 bits
• Fast clock speeds to 166 MHz in LVTTL/ LVCMOS
• Fast clock to data access: 3.5/ 3.8/ 4/ 5 ns
• Fast OEaccess time: 3.5/ 3.5/ 3.8/ 4 ns
• Fully synchronous register-to-register operation
• Single register ‘flow-through’ mode
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/ O operation with separate V
DDQ
• Automatic power down: 10 mW typical standby power
• NTD™ pipeline architecture available
(AS7C3128KNTD32/ 36)
• Single cycle de-select
• Pentium® compatible architecture and timing
• Synchronous and asynchronous output enable control
• Economical 100-pin TQFP package
Logic block diagram
Pin arrangement
lbo
clk
adv
clk
ce
clr
burst logic
adsc
adsp
128k×32/ 36
memory
17
15
17
17
d
ce
clk
q
a[16:0]
array
address
register
DQPb/ NC
DQb
DQPc/ NC
DQc
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
DQb
DQc
3
36
36
gwe
bwe
V
V
4
DDQ
DDQ
d
q
q
q
q
V
V
5
dqd
SSQ
SSQ
bw
d
DQb
DQb
DQb
DQb
DQc
DQc
DQc
DQc
6
byte write
registers
clk
7
8
9
d
dqc
V
V
10
11
bw
c
SSQ
SSQ
DDQ
byte write
registers
V
V
DDQ
DQb
DQb
DQc 12
DQc 13
FT 14
TQFP 14x20mm
clk
d
V
SS
dqb
bw
b
V
V
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
DD
DD
byte write
registers
clk
V
V
DD
DD
V
ZZ
SS
DQa
DQa
DQd
d
DQd
dqa
byte write
registers
bw
a
4
V
V
DDQ
DDQ
V
V
SSQ
SSQ
clk
d
DQa
DQa
DQa
DQa
DQd
DQd
DQd
DQd
ce0
ce1
ce2
q
q
oe
output
registers
le
enable
input
registers
clk
register
V
V
SSQ
SSQ
ce
V
V
DDQ
clk
DDQ
clk
DQa
DQd
DQa
DQd
d
enable
delay
DQPa/ NC
DQPd/ NC 30
power
down
zz
oe
register
clk
36
ft
data [35:0]
Note: Pins 1,30,51,80 are NC for ×32
Selection guide
AS7C3128PFS32/ 36A AS7C3128PFS32/ 36A AS7C3128PFS32/ 36A AS7C3128PFS32/ 36A
3.5
6
166.7
-3.8
6.7
150
-4
7.5
133.3
-5
10
100
Units
ns
MHz
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access
time
3.5
3.8
4
5
ns
Maximum operating current
Maximum standby current
Maximum CMOS standby current
(DC)
350
60
325
60
300
60
250
60
mA
mA
5
5
5
5
mA
6/ 8/ 00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS7C3128PFS32/ 36A
®
Functional description
The AS7C37C3128PFS32/ 36A family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory
(SRAM) organized as 131,072 words × 32 or 36 bits and incorporates a two stage register-register pipeline for highest
frequency on any given technology.
Timing for this device is compatible with existing Pentium synchronous cache specifications. This architecture is suited for
ASIC, DSP (TMS320C6X), and PowerPC based systems in computing, datacomm, instrumentation, and telecommunications
systems. When using pipeline burst SRAMs, any turnaround from read-to-write and write-to-read, required the insertion of
two dead cycles. When reading data, a two cycle latency until data valid exists due to the nature of the dual register
architecture. When writing, data, address and controls are all presented simultaneously. Therefore two dead cycles are required
to clear the read pipeline before a write can occur. In a write-to-read transition, two dead cycles are again produced due to the
pipeline read latency. These penalties are eliminated in the AS7C3128KNTD32/ 36 architecture device.
Fast cycle times of 6/ 6.7/ 7.5/ 10 ns with clock access times (tCD) of 3.5/ 3.5/ 3.8/ 4 ns enable 167, 150, 133 and 100 MHz
bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the
controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent
internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a
read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when WE is sampled High, ADV is sampled Low, and both address strobes are High. Burst operation is
selectable with the MODE input. With MODE unconnected or driven High, burst operations use a Pentium count sequence.
With MODE driven LOW the device uses a linear count sequence, suitable for PowerPC and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enableGWE
writes all 32 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be
written by asserting BWE and the appropriate individual byte BW signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low.
Address is incremented internally to the next burst of address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and
ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WEsignals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C3128K36P family operates from a 3.3V supply. I/ O’s use a separate power supply that can operate at 2.5V or 3.3V.
This device is available in a 100-pin 14×20 mm TQFP package.
Capacitance
Parameter
Symbol
Signals
Address and control pins
I/ O pins
Test conditions
V = 0V
Max
5
7
Unit
pF
pF
Input capacitance
I/ O capacitance
C
IN
in
C
V = Vout = 0V
I/ O
in
Write enable truth table (per byte)
GWE
BWE
BWn
X
WRITEn
L
X
T
X
L
L
T
H
H
X
F
F †
H
L
H
Key: X = Don’t Care, L = Low, H = High.
†
Valid read.
2
ALLIANCE SEMICONDUCTOR
6/ 8/ 00
AS7C3128PFS32/ 36A
®
Signal descriptions
Signal
I/ O Properties
Description
Clock. All inputs except OE are synchronous to this clock.
CLK
I
I
CLOCK
SYNC
A0–A16
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
DQ[a,b,c,d] I/ O SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the SYNCHRONOUS TRUTH TABLE for more
information.
CE0
I
SYNC
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock edges
when ADSC is active or when CE1 and ADSP are active.
CE1, CE2
I
SYNC
ADSP
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode.
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/ write.
SYNC default Global write enable. Asserted LOW to write all 36 bits. When High, BWE and WE0–WE3
= HIGH control write enable. This signal is internally pulled High.
SYNC default Byte write enable. Asserted LOW with GWE = HIGH to enable effect of WE0–WE3 inputs.
GWE
BWE
I
I
= LOW
This signal is internally pulled Low.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
BW[a,b,c,d] I
SYNC
Asynchronous output enable. I/ O pins are driven when OE is active and the chip is
synchronously enabled.
OE
I
I
ASYNC
STATIC default Count mode. When driven High, count sequence follows Intel XOR convention. When
LBO
= HIGH
STATIC
ASYNC
driven Low, count sequence follows linear convention. This signal is internally pulled High.18
Flow-through mode.When low, enables single register flow-through mode. Connect to V
DD
FT
ZZ
I
I
if unused or for pipelined operation.
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/ O pins)
Power dissipation
Symbol
VDD, V
Min
–0.5
–0.5
–0.5
–
Max
Unit
V
V
V
W
+4.6
+4.6
VDDQ + 0.5
1.2
DDQ
V
IN
V
IN
PD
DC output current
Storage temperature (plastic)
Temperature under bias
IOUT
Tstg
Tbias
–
–65
–65
30
+150
+135
mA
oC
oC
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions may affect reliability.
6/ 8/ 00
ALLIANCE SEMICONDUCTOR
3
AS7C3128PFS32/ 36A
®
Synchronous truth table
†
CE0
H
L
CE1
X
L
CE2
X
X
X
H
H
L
ADSP ADSC ADV
n
OE
X
X
X
X
X
L
Address accessed CLK
Operation
X
L
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
F
F
T
T
T
T
T
NA
L to H Deselect
X
L
NA
Lto H Deselect
L
L
H
L
NA
Lto H Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Lto H Deselect
L
H
L
NA
Lto H Deselect
L
X
X
L
External
External
External
External
Next
Lto H Begin read
Lto H Begin read
Lto H Begin read
Lto H Begin read
Lto H Cont. read
Lto H Cont. read
Lto H Suspend read
Lto H Suspend read
Lto H Cont. read
Lto H Cont. read
L to H Suspend read
L to H Suspend read
Lto H Begin write
Lto H Cont. write
Lto H Cont. write
Lto H Suspend write
L to H Suspend write
L
L
L
H
L
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
L
L
H
L
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
L
H
L
Next
H
H
L
Current
Current
Next
H
L
L
H
L
Next
H
H
X
L
Current
Current
External
Next
H
X
X
X
H
H
X
H
X
H
X
X
X
X
H
H
H
H
L
Next
H
H
Current
Current
Key: X = Don’t Care, L = Low, H = High.
†
See Write enable truth table for more information.
Recommended operating conditions
Parameter
Symbol
VDD
GND
Min
3.135
0.0
Nominal
3.3
0.0
Max
3.6
0.0
Unit
V
V
Supply voltage
VDDQ
GNDQ
2.35
0.0
2.5 or 3.3
0.0
–
–
–
3.6
0.0
4.5
0.8
VDDQ + 0.5
0.8
70
V
V
V
V
I/ O supply voltage
Address and
V
2.0
IH
–0.5*
2.0
control pins
V
IL
Input voltages
V
V
IH
I/ O pins
V
-0.5*
0
–
–
IL
Ambient operating temperature
TA
°C
* V min = –2.0V for pulse width less than 0.2 x t
IL
.
RC
DC electrical characteristics over operating range
-166
-150
-133
-100
Parameter
Symbol Test conditions
Min Max Min Max Min Max Min Max Unit
Input leakage
current
| ILI |
| ILO
VDD = Max, V = GND to VDD
–
–
2
2
–
–
2
2
–
–
2
2
–
–
2
2
µA
µA
in
Output leakage
current
OE ≥ VIH, VDD = Max,
|
Vout = GND to VDD
4
ALLIANCE SEMICONDUCTOR
6/ 8/ 00
AS7C3128PFS32/ 36A
®
-166
-150
-133
-100
Parameter
Symbol Test conditions
Min Max Min Max Min Max Min Max Unit
Operating power
supply current
CE = V , CE = V , CE = V ,
IL
IH
IL
ICC
ISB
–
–
–
350
60
5
–
–
–
325
60
5
–
–
–
300
60
5
–
–
–
250 mA
60 mA
f = fmax, out
I
= 0 mA
f = fmax
f = 0
≤ 0.2V or ≥ VDD - 0.2V
Standby power
supply current
ISB1
5
mA
IN
V
IOL = 8 mA, VDDQ = 3.6V
IOH = –8 mA, VDDQ = 3.0V
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
OL
Output voltage
V
2.4
2.4
2.4
2.4
OH
Timing characteristics over operating range
-3.5
-3.8
-4
-5
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Clock frequency
Cycle time (pipelined mode)
Clock access time (pipelined mode)
FMAX
tCYC
tCD
-
6
-
-
-
0
1.5
1
-
-
166
-
3.5
6
3.5
-
-
-
6.6
-
-
-
0
1.5
1
-
-
150
-
3.8
6.6
3.5
-
-
-
7.5
-
-
-
133
-
10
-
-
-
0
2
2
-
-
-
3
3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
100 MHz 1
-
4
7.5
3.8
-
-
-
4
3.5
2
-
-
-
-
-
-
-
-
-
-
5
10
4
-
-
-
4
3.5
2.5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock access time (flow-through mode) tCDF
Output enable Low to data valid
Clock High to output Low Z
Data output hold from clock High
Output enable Low to output Low Z
Output enable High to output High Z
Clock High to output High Z
Clock High to output High Z
Clock High pulse width
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tHZCN
tCH
0
8
8
8
8
8
1.5
1.5
-
-
-
2.8
2.8
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
-
-
3
2.5
1.5
-
-
-
-
-
-
-
3.5
3
1.5
-
-
-
-
-
-
-
-
-
ns 1,9
ns
ns
2.4
2.4
1
1
1
2.6
2.6
1.3
1.3
1.3
1.3
0.5
0.5
0.5
0.5
1.5
1.5
Clock Low pulse width
Address and Control setup to clock High tAS
Data setup to clock High
tCL
-
-
ns
tDS
tWS
tCSS
tAH
tDH
tWH
tCSH
tR
-
ns
Write setup to clock High
Chip select setup to clock High
Address hold from clock High
Data hold from clock High
Write hold from clock High
Chip select hold from clock High
Output rise time (0 pF load)
Output fall time (0 pF load)
See “Notes” on page 9.
-
ns
1
-
ns
0.5
0.5
0.5
0.5
1.5
1.5
-
ns
-
-
-
-
-
-
-
-
-
ns
-
ns
-
-
-
-
ns
-
-
V/ ns 1
V/ ns 1
tF
-
-
Key to switching waveforms
Rising input
Falling input
Undefined/ don’t care
6/ 8/ 00
ALLIANCE SEMICONDUCTOR
5
AS7C3128PFS32/ 36A
®
Timing waveform of read cycle
t
t
CYC
t
CH
CL
CLK
t
SS
t
SH
ADSP
t
SS
t
SH
ADSC
t
AS
LOAD NEW ADDRESS
t
AH
A1
A2
A3
Address
t
WS
t
WH
GWE, BWE
t
CSS
t
CSH
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
CD
t
HZOE
t
LZOE
t
t
OH
ADV INSERTS WAIT STATES
t
t
HZC
OE
LZC
Q(A1)
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)
D
OUT
(pipelined mode)
t
OE
t
LZOE
Q(A1)
Q(A2) Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11) Q(A3)
Q(A3Ý01) Q(A3Ý10)
Q(A3Ý11)
D
OUT
(flow-through mode)
t
HZC
t
CDF
Note: = XOR when MODE = High/ No Connect; = ADD when MODE = Low. Refer to Burst Sequence Table.
[0:3] is don’t care.
6
ALLIANCE SEMICONDUCTOR
6/ 8/ 00
AS7C3128PFS32/ 36A
®
Timing waveform of write cycle
t
t
CYC
CL
t
CH
CLK
t
SS
t
SH
ADSP
ADSC
t
SS
t
SH
ADSC LOADS NEW ADDRESS
A3
t
AS
t
AH
A1
A2
Address
t
WS
t
WH
WE
BW[a:d]
t
CSS
t
CSH
CE0, CE2
CE1
t
ADVS
ADV SUSPENDS BURST
t
ADVH
ADV
OE
t
DS
t
DH
D(A1)
D(A2)
D(A2Ý01) D(A2Ý01) D(A2Ý10) D(A2Ý11) D(A3)
D(A3Ý01) D(A3Ý10)
Data In
Note: = XOR when MODE = High/ No Connect; = ADD when MODE = Low. Refer to Burst Sequence Table.
6/ 8/ 00
ALLIANCE SEMICONDUCTOR
7
AS7C3128PFS32/ 36A
®
Timing waveform of read/ write cycle
t
t
CYC
t
CH
CL
CLK
t
SS
t
SH
ADSP
t
AS
t
AH
A2
A3
Address
A1
t
WS
t
WH
WE
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A2)
HZOE
D
IN
t
t
OH
t
t
LZOE
LZC
t
t
CD
OE
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10) Q(A3Ý11)
D
OUT
(pipeline mode)
t
CDF
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
D
OUT
(flow-through mode)
Note: = XOR when MODE = High/ No Connect; = ADD when MODE = Low. Refer to Burst Sequence Table.
8
ALLIANCE SEMICONDUCTOR
6/ 8/ 00
AS7C3128PFS32/ 36A
®
Notes
1
2
3
4
This parameter is guaranteed but not tested.
6
7
8
9
I
given with no output loading. I increases with faster cycle times
CC
CC
and greater output loading.
For test conditions, see AC Test Conditions, Figures A, B, C.
Transitions are measured ±500 mV from steady state voltage. Output
loading specified with C = 5 pF as in Figure C.
This parameter is sampled and not 100% tested.
This is a synchronous device. All addresses must meet the specified setup
and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times with stable logic levels for all rising
edges of CLK when chip is enabled.
L
t
is less than t
; and t
is less than t at any given temperature
HZC LZC
HZOE
and voltage.
LZOE
t
is a‘no load’ parameter to indicate exactly when SRAM outputs
HZCN
have stopped driving.
5
Typical values measured at 3.3V, 25°C and 10 ns cycle time.
AC test conditions
• Output Load: see Figure B,
except for
t
, t
, t
, tHZC see Figure C.
LZC LZOE HZOE
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V
317Ω
5 pF*
Z =50Ω
50Ω
0
D
out
D
+3.0V
V =1.5V
out
L
90%
10%
90%
10%
30 pF*
351Ω
GND
*including scope
and jig capacitance
GND
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
AS7C3128PFS32/ 36A ordering information
Package Functionality
166 MHz
AS7C3128PFS32/ 36AP-
3.5TQC
150 MHz
AS7C3128PFS32/ 36A-
3.8TQC
133 MHz
100 MHz
TQFP
TQFP
PBSRAM
PBSRAM
AS7C3128PFS32/ 36A-4TQCAS7C3128PFS32/ 36A-5TQC
AS7C3128PFS32/ 36A-4TQCAS7C3128PFS32/ 36A-5TQC
AS7C3128PFS32/ 36A-
3.5TQC
AS7C3128PFS32/ 36A-
3.8TQC
AS7C3128K32P and AS7C3128PFS32/ 36A part numbering system
AS7C
3
128K36
P
–XX
XX
C
Timing
SRAM
prefix
Operating
voltage
Part number,
organization
Package:
TQ = TQFP
Commercial temperature,
0°C to 70 °C
NTD=NTD timing access time (ns)
P=PBSRAM
NTD is a trademark of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corporation.
6/ 8/ 00
ALLIANCE SEMICONDUCTOR
9
相关型号：
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