AS7C33128FT36B-10TQI [ALSC]
3.3V 128K x 32/36 Flow Through Synchronous SRAM; 3.3V 128K X 32/36流通过同步SRAM
| 型号： | AS7C33128FT36B-10TQI |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 128K x 32/36 Flow Through Synchronous SRAM |
| 文件： | 总19页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS7C33128FT32B
AS7C33128FT36B
February 2005
®
3.3V 128K × 32/36 Flow Through Synchronous SRAM
Features
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Organization: 131,072 words × 32 or 36 bits
• Fast clock to data access: 6.5/7.5/8.0/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and Global write
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
• Snooze mode for reduced power standby
• Common data inputs and data outputs
DDQ
Logic block diagram
LBO
CLK
ADV
CLK
CE
Burst logic
ADSC
ADSP
CLR
128K × 32/36
Memory
array
19
17
19
19
D
CE
CLK
Q
A
[18:0]
Address
register
36/32
36/32
GWE
BWE
BWd
D
Q
DQd
Byte write
registers
CLK
D
Q
DQc
Byte write
registers
BWc
BWb
BWa
CLK
D
Q
DQb
Byte write
registers
CLK
D
Q
DQa
Byte write
4
registers
CLK
CE0
CE1
OE
Output
buffer
D
Q
Q
CE2
Input
registers
CLK
Enable
register
CE
CLK
D
Enable
Power
down
delay
register
CLK
ZZ
36/32
OE
DQ[a:d]
Selection guide
–65
-75
8.5
7.5
250
85
-80
10
-10
12
Units
ns
Minimum cycle time
7.5
6.5
275
90
Maximum clock access time
Maximum operating current
Maximum standby current
8.0
215
75
10.0
185
75
ns
mA
mA
mA
Maximum CMOS standby current (DC)
30
30
30
30
2/8/05; v.1.2
Alliance Semiconductor
P. 1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128FT32B
AS7C33128FT36B
®
4 Mb Synchronous SRAM products list1,2
Org
Part Number
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
Speed
256KX18
128KX32
128KX36
256KX18
128KX32
128KX36
256KX18
128KX32
128KX36
256KX18
128KX32
128KX36
256KX18
128KX32
128KX36
AS7C33256PFS18B
AS7C33128PFS32B
AS7C33128PFS36B
AS7C33256PFD18B
AS7C33128PFD32B
AS7C33128PFD36B
AS7C33256FT18B
AS7C33128FT32B
AS7C33128FT36B
AS7C33256NTD18B
AS7C33128NTD32B
AS7C33128NTD36B
AS7C33256NTF18B
AS7C33128NTF32B
AS7C33128NTF36B
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
1
TM
NTD -PL
:
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
Flow-through Burst Synchronous SRAM with NTD
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
2/8/05; v.1.2
Alliance Semiconductor
P. 2 of 19
AS7C33128FT32B
AS7C33128FT36B
®
Pin arrangement
DQP /NC
DQP /NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
b
c
DQ
DQ
2
b7
b6
DDQ
SSQ
c0
c1
DDQ
SSQ
DQ
DQ
3
V
V
4
V
V
5
DQ
DQ
6
b5
c2
DQ
DQ
7
b4
c3
DQ
DQ
8
b3
DQ
c4
DQ
9
b2
c5
V
V
V
V
10
11
12
13
SSQ
DDQ
SSQ
DDQ
DQ
DQ
b1
c6
DQ
DQ
b0
c7
V
NC
NC 14
SS
V
15
DD
TQFP 14 × 20 mm
VDD
ZZ
NC 16
V
17
18
19
20
21
22
23
24
25
26
27
28
29
SS
d0
d1
DQ
DQ
a7
DQ
DQ
DDQ
a6
DDQ
SSQ
V
V
V
V
SSQ
DQ
DQ
a5
d2
d3
d4
d5
DQ
DQ
a4
DQ
DQ
DQ
V
a3
DQ
a2
V
V
SSQ
DDQ
SSQ
V
DDQ
DQ
DQ
a1
d6
d7
DQ
DQ
a0
DQP /NC
DQP /NC 30
a
d
Note: Pins 1,30,51,80 are NC for ×32
2/8/05; v.1.2
Alliance Semiconductor
P. 3 of 19
AS7C33128FT32B
AS7C33128FT36B
®
Functional description
The AS7C33128FT32B/36B is a high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized
as 131,072 words × 32 or 36 bits.
Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory
expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP).
The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is
ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for
the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With
LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count
sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
32/36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented
internally to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C33128FT32B and AS7C33128FT36B family operates from a core 3.3V power supply. I/Os use a separate power supply that can
operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package.
TQFP capacitance
Parameter
Input capacitance
Symbol
Test conditions
VIN = 0V
Min
Max
Unit
pF
*
CIN
-
-
5
7
*
I/O capacitance
CI/O
VOUT = 0V
pF
*Guaranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
Typical
40
Units
°C/W
°C/W
1–layer
4–layer
θJA
θJA
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
22
Thermal resistance
θJC
8
°C/W
(junction to top of case)1
1 This parameter is sampled
2/8/05; v.1.2
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P. 4 of 19
AS7C33128FT32B
AS7C33128FT36B
®
Signal descriptions
Description
Pin
CLK
I/O Properties
I
I
CLOCK
SYNC
SYNC
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
A,A0,A1
DQ[a,b,c,d]
I/O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE0
I
I
SYNC
SYNC
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 32/36 bits. When high, BWE and BW[a:d] control write
enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,
the cycle is a read cycle.
BW[a,b,c,d]
I
SYNC
OE
I
I
ASYNC
STATIC
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
LBO
ZZ
I
-
ASYNC
-
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
NC
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
2/8/05; v.1.2
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P. 5 of 19
AS7C33128FT32B
AS7C33128FT36B
®
1
Write enable truth table (per byte)
Function
GWE BWE
BWa
X
BWb
X
BWc
BWd
X
L
H
H
H
H
H
X
L
L
L
H
L
X
L
Write All Bytes
L
L
L
Write Byte a
L
H
H
L
H
Write Byte c and d
H
H
L
X
X
X
H
X
Read
H
H
H
1 Key: X = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal.
Asynchronous Truth Table
Operation
Snooze mode
ZZ
H
L
OE
X
I/O Status
High-Z
L
Dout
Read
L
H
High-Z
Write
L
X
Din, High-Z
High-Z
Deselected
L
X
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Interleaved burst address (LBO = 1)
A1 A0 A1 A0 A1 A0 A1 A0
Linear burst address (LBO = 0)
A1 A0 A1 A0 A1 A0 A1 A0
1st Address
2nd Address
3rd Address
4th Address
0 0
0 1
1 0
1 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
1st Address
2nd Address
3rd Address
4th Address
0 0
0 1
1 0
1 1
0 1
1 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
2/8/05; v.1.2
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P. 6 of 19
AS7C33128FT32B
AS7C33128FT36B
®
Synchronous truth table[4]
[2]
CE01
H
L
CE1
X
L
CE2
X
X
X
H
H
L
ADSP ADSC ADV WRITE
OE
X
X
X
X
X
L
Address accessed
NA
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
NA
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
L
H
L
Next
Hi−Z
Q
H
H
L
Current
Current
Next
H
L
Hi−Z
Q
L
H
L
Next
Hi−Z
Q
H
H
X
L
Current
Current
External
Next
H
X
X
X
X
X
Hi−Z
3
D
X
H
X
H
X
X
X
X
H
H
H
H
L
D
D
D
D
L
L
Next
H
H
L
Current
Current
L
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE
HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
2/8/05; v.1.2
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P. 7 of 19
AS7C33128FT32B
AS7C33128FT36B
®
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–0.5
–
Max
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
V
, V
+4.6
DD
DDQ
V
V
+ 0.5
DD
V
IN
V
V
+ 0.5
V
IN
DDQ
P
1.8
W
D
DC output current
I
–
50
mA
°C
°C
OUT
Storage temperature (plastic)
Temperature under bias
T
–65
–65
+150
+135
stg
T
bias
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other con-
ditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
3.135
0
Nominal
Max
3.465
3.465
0
Unit
V
3.3
3.3
0
VDDQ
Vss
V
V
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
Min
3.135
2.375
0
Nominal
Max
3.465
2.625
0
Unit
V
VDD
VDDQ
Vss
3.3
2.5
0
V
V
2/8/05; v.1.2
Alliance Semiconductor
P. 8 of 19
AS7C33128FT32B
AS7C33128FT36B
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current†
Output leakage current
Sym
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
|ILI|
2
2
|ILO
|
-2
µA
2*
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
VIL
V
V
2*
V
DDQ+0.3
Address and control pins
I/O pins
-0.3**
-0.5**
2.4
0.8
0.8
–
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
V
V
–
0.4
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current†
Output leakage current
Sym
Conditions
Min
-2
Max
Unit
µA
µA
V
|ILI|
VDD = Max, 0V < VIN < VDD
2
2
|ILO
|
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
-2
1.7*
1.7*
-0.3**
-0.3**
1.7
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
VIL
V
DDQ+0.3
V
Address and control pins
I/O pins
0.7
0.7
–
V
V
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
V
–
0.7
V
† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
*
V
max < VDD +1.5V for pulse width less than 0.2 X t
CYC
IH
**
V
min = -1.5 for pulse width less than 0.2 X t
CYC
IL
IDD operating conditions and maximum limits
Parameter
Sym
Conditions
-65
-75
-80
-10
Unit
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
,
Operating power supply current1
ICC
275
250
215
75
185
mA
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or >
V
– 0.2V, Deselected,
DD
ISB
90
85
75
f = fMax, ZZ < VIL
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Standby power supply current
mA
ISB1
ISB2
30
30
30
30
30
30
30
30
Deselected, f = f , ZZ
≥
V
– 0.2V,
Max
DD
all VIN ≤ VIL or ≥ VIH
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
2/8/05; v.1.2
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P. 9 of 19
AS7C33128FT32B
AS7C33128FT36B
®
Timing characteristics over operating range
–65
-75
-80
–10
Notes
1
Parameter
Sym
Min Max Min Max Min Max Min Max Unit
Cycle time
t
7.5
–
–
6.5
3.5
–
8.5
–
–
7.5
3.5
–
10
–
–
8.0
4.0
–
12
–
–
10
4.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYC
Clock access time
t
CD
Output enable LOW to data valid
Clock HIGH to output Low Z
Data output invalid from clock HIGH
Output enable LOW to output Low Z
Output enable HIGH to output High Z
Clock HIGH to output High Z
Output enable HIGH to invalid output
Clock HIGH pulse width
t
–
–
–
–
OE
t
2.5
2.5
0
2.5
2.5
0
2.5
2.5
0
2.5
2.5
0
2,3,4
2
LZC
t
–
–
–
–
OH
t
–
–
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.0
3.0
–
–
3.5
3.5
–
–
4.0
4.0
–
–
5.0
5.0
–
t
–
–
–
–
HZC
t
0
0
0
0
OHOE
t
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
3.0
3.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
4.0
4.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
4.0
4.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
5
5
CH
Clock LOW pulse width
t
t
t
–
–
–
–
CL
AS
DS
Address setup to clock HIGH
Data setup to clock HIGH
–
–
–
–
6
–
–
–
–
6
Write setup to clock HIGH
t
–
–
–
–
6,7
6,8
6
WS
Chip select setup to clock HIGH
Address hold from clock HIGH
Data hold from clock HIGH
Write hold from clock HIGH
Chip select hold from clock HIGH
ADV setup to clock HIGH
t
–
–
–
–
CSS
t
–
–
–
–
AH
DH
WH
t
–
–
–
–
6
t
–
–
–
–
6,7
6,8
6
t
–
–
–
–
CSH
t
–
–
–
–
ADVS
ADSP setup to clock HIGH
ADSC setup to clock HIGH
ADV hold from clock HIGH
ADSP hold from clock HIGH
ADSC hold from clock HIGH
1 See “Notes” on page 16.
t
–
–
–
–
6
ADSPS
ADSCS
t
–
–
–
–
6
t
–
–
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
–
–
6
t
–
–
–
–
6
Snooze Mode Electrical Characteristics
Description
Conditions
Symbol
Min
Max
Units
Current during Snooze Mode
ZZ active to input ignored
ZZ > V
I
30
mA
IH
SB2
PDS
PUS
t
t
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
t
2
ZZI
t
0
RZZI
2/8/05; v.1.2
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Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
t
CYC
t
t
CL
CH
CLK
t
t
ADSPS
ADSPH
ADSP
t
t
ADSCS
ADSCH
ADSC
Address
LOAD NEW ADDRESS
A3
t
t
t
AS
AH
A1
A2
WS
t
WH
GWE, BWE
t
t
CSS
CSH
CE0, CE2
CE1
t
t
ADVS
ADVH
ADV
OE
ADV inserts wait states
t
OE
t
HZOE
t
OH
t
LZOE
Q(A3Ý11)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A1)
Dout
t
CD
t
HZC
Read
Q(A1)
Suspend Read BurstReadBurstRead Suspend BurstRead Read BurstRead BurstReadBurstRead
2Ý01
) Q(A
2Ý10
2Ý11
3Ý01
) Q(A
3Ý10 3Ý11
) Q(A )
Read
Q(A2) Q(A
)
Read
2Ý10
)
Q(A
)
Q(A3) Q(A
DSEL
Q(A1)
Q(A
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
2/8/05; v.1.2
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Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
tAS
tAH
A1
A3
A2
Address
tWS
tWH
BWE
BW[a:d]
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV SUSPENDS BURST
ADV
OE
tDS
tDH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Din
ADV
Burst
Write
Read
Q(A1)
Suspend
Write
D(A1)
Read
Q(A2)
Suspend
Write
ADV
Burst
Write
Suspend
Write
ADV
Burst
Write
ADV
Burst
Write
Write
3
D(A )
Burst
Write
3Ý01
D(A )
2
2Ý01
D(A )
D(A
)
3Ý10
D(A
)
2Ý01
2Ý10
2Ý11
D(A )
D(A
)
D(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
2/8/05; v.1.2
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tAS
tAH
A2
A3
A1
Address
tWS
tWH
BWE
BW[a:d]
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tDH
tDS
Din
D(A2)
tOE
tCD
tLZC
tOH
tHZOE
tLZOE
Dout
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Suspend
Write
Read
Q(A3)
ADV
Burst
Read
ADV
Burst
Read
ADV
Burst
Read
Suspend
Read
3Ý11
Q(A )
2
D(A )
3Ý01
3Ý10
3Ý11
Q(A )
Q(A
)
Q(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
2/8/05; v.1.2
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCYC
tCH
tCL
CLK
tADSCS
tADSCH
ADSC
tAS
tAH
A9
A10
A5
A4
A7
A8
A3
A6
A1
A2
ADDRESS
tWS
tWH
BWE
BW[a:d]
tCSS
tCSH
CE0,CE2
CE1
OE
tCD
tOE
tOH
tHZOE
tLZOE
Q(A2)
Q(A9)
Q(A1)
Q(A3)
Q(A10)
Q(A4)
Dout
Din
tDH
tDS
D(A5)
D(A6)
D(A7)
D(A8)
READ
Q(A10)
WRITE
D(A7)
READ READ READ
Q(A1) Q(A2) Q(A3)
WRITE
D(A6)
WRITE
D(A8)
READ
Q(A9)
READ
Q(A4)
WRITE
D(A5)
Note: ADV is don’t care here.
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Timing waveform of power down cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPS
ADSP
ADSC
A2
A1
ADDRESS
tWH
tWS
BWE
BW[a:d]
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
tLZOE
Din
tHZOE
tHZC
Dout
Q(A2)
Q(A1)
tPUS
Q(A2(Ý01))
tPDS
ZZ Recovery Cycle
Normal Operation Mode
ZZ
ZZ Setup Cycle
tZZI
tRZZI
ISB2
Isupply
Sleep
State
READ
READ
READ
READ
Q(A1) Q(A1Ý01)
Q(A2) Q(A2Ý01)
2/8/05; v.1.2
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AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω / 1667Ω
Z0 = 50Ω
50
Ω
DOUT
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
+3.0V
DOUT
90%
10%
90%
10%
5 pF*
353Ω / 1538Ω
30 pF*
GND
*including scope
and jig capacitanc
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load (B)
Notes
1
2
3
4
5
6
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
HZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
,
BWE
,
BW[a:d].
CE2
Chip select refers to CE0
,
CE1
,
2/8/05; v.1.2
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Package Dimensions
100-pin quad flat pack (TQFP)
Hd
D
c
α
b
e
L1
L
A1 A2
He
E
TQFP
Min
0.05
1.35
0.22
0.09
Max
0.15
1.45
0.38
0.20
A1
A2
b
c
D
13.90 14.10
19.90 20.10
0.65 nominal
15.85 16.15
21.80 22.20
E
e
Hd
He
L
0.45
1.00 nominal
0° 7°
0.75
L1
α
Dimensions in
millimeters
2/8/05; v.1.2
Alliance Semiconductor
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Ordering information
Package Width
–65
-75
–80
–10
AS7C33128FT32B-
65TQC
AS7C33128FT32B-
75TQC
AS7C33128FT32B-
80TQC
AS7C33128FT32B-
10TQC
TQFP
TQFP
TQFP
TQFP
x32
x32
x36
x36
AS7C33128FT32B-
65TQI
AS7C33128FT32B-
75TQI
AS7C33128FT32B-
80TQI
AS7C33128FT32B-
10TQI
AS7C33128FT36B-
65TQC
AS7C33128FT36B-
75TQC
AS7C33128FT36B-
80TQC
AS7C33128FT36B-
10TQC
AS7C33128FT36B-
65TQI
AS7C33128FT36B-
75TQI
AS7C33128FT36B-
80TQI
AS7C33128FT36B-
10TQI
Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C33128FT32B-65TQCN)
Part numbering guide
AS7C
33
128
FT
32/36
B
–XX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor SRAM Prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 128 = 128K
4. Flowthrough mode
5. Organization: 32 = X32; 36 = X36
6. Production version: B= product revision
7. Clock access time: [-65 = 6.5 ns; -75 = 7.5 ns; -80 = 8.0 ns; -10 = 10.0]
8. Package type: TQ = TQFP
9. Operating temperature: C = Commercial (0° C to 70° C); I = Industrial (-40° C to 85° C)
10. N = Lead free part
2/8/05; v.1.2
Alliance Semiconductor
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®
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33128FT32B
AS7C33128FT36B
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Document Version: v.1.2
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
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