AS7C33128NTF18B-75TQC [ALSC]
3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD; 3.3V 128K ×18穿透液同步SRAM与NTD
| 型号： | AS7C33128NTF18B-75TQC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD |
| 文件： | 总19页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2005
AS7C33128NTF18B
®
3.3V 128K x 18 Flowthrough Synchronous SRAM with NTDTM
Features
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• Self-timed write cycles
• Organization: 131,072 words × 18 bits
™
• NTD architecture for efficient bus operation
• Fast clock to data access: 7.5/8.0/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
DDQ
• Interleaved or linear burst modes
• Snooze mode for standby operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
Logic block diagram
17
17
A[16:0]
Q
D
Address
register
burst logic
CLK
D
Q
CE0
CE1
CE2
Write delay
addr. registers
CLK
17
R/W
BWa
BWb
Control
logic
CLK
ADV / LD
128K x 18
LBO
ZZ
SRAM
array
CLK
18
18
DQ [a,b]
Data
input
register
D
Q
18
18
CLK
18
CLK
CEN
Output
buffer
OE
18
OE
DQ [a,b]
Selection guide
-75
8.5
7.5
260
110
30
-80
-10
12
Units
ns
Minimum cycle time
10
8.0
230
100
30
Maximum clock access time
Maximum operating current
Maximum standby current
10
ns
200
90
mA
mA
mA
Maximum CMOS standby current (DC)
30
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P. 1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128NTF18B
®
2 Mb Synchronous SRAM products list1,2
3
Org
Part Number
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
Speed
128KX18
64KX32
AS7C33128PFS18B
AS7C3364PFS32B
AS7C3364PFS36B
AS7C33128PFD18B
AS7C3364PFD32B
AS7C3364PFD36B
AS7C33128FT18B
AS7C3364FT32B
AS7C3364FT36B
AS7C33128NTD18B
AS7C3364NTD32B
AS7C3364NTD36B
AS7C33128NTF18B
AS7C3364NTF32B
AS7C3364NTF36B
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.0/10 ns
64KX36
128KX18
64KX32
64KX36
128KX18
64KX32
FT
64KX36
128KX18
64KX32
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
64KX36
128KX18
64KX32
7.5/8.0/10 ns
64KX36
7.5/8.0/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
3 Refer corresponding product datasheets for the latest information on Clock Speed and Clock Access Time availability.
PL-SCD
PL-DCD
FT
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
1
TM
NTD -PL
:
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
Flow-through Burst Synchronous SRAM with NTD
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
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AS7C33128NTF18B
®
100-pin TQFP - top view
1
2
3
4
5
6
7
8
9
NC
NC
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
NC
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDQ
VSSQ
NC
NC
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
NC
VDD
NC
VSS
10
11
12
TQFP 14 x 20mm
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
27
28
29
30
NC
NC
NC
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AS7C33128NTF18B
®
Functional Description
The AS7C33128NTF18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM)
organized as 131,072 words × 18 bits and incorporates a LATE Write.
™
This variation of the 2Mb+ synchronous SRAM uses the No Turnaround Delay (NTD ) architecture, featuring an enhanced
write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for one 'dead' cycle for valid data to become available. This dead cycle can significantly reduce overall
bandwidth for applications requiring random access or read-modify-write operations.
™
NTD devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow-
through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.
™
With NTD , write and read operations can be used in any order without producing dead bus cycle.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write
operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by
any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33128NTF18B operates with a 3.3V ± 5% power supply for the device core (V ). DQ circuits use a separate
DD
power supply (V
) that operates across 2.5V or 3.3V ranges. These devices are available in a 100-pin TQFP package.
DDQ
TQFP Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
Test conditions
V = 0V
Min
Max
Unit
pF
*
C
-
-
5
7
IN
in
*
C
V = V = 0V
pF
I/O
in
out
*Guranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
Typical
40
Units
°C/W
°C/W
1–layer
4–layer
θJA
θJA
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
22
Thermal resistance
θJC
8
°C/W
(junction to top of case)1
1 This parameter is sampled
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AS7C33128NTF18B
®
Signal descriptions
Signal
CLK
I/O Properties
Description
I
I
CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN
SYNC
SYNC
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
A, A0, A1
DQ[a,b]
I
I/O
CE0, CE1,
CE2
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
I
I
I
SYNC
SYNC
SYNC
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. When low, a new address is loaded.
ADV/LD
R/W
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
BW[a,b]
OE
I
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
STATIC
LBO
driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
No connects.
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
Burst order
Interleaved burst order LBO = 1
A1A0 A1A0 A1A0 A1A0
Linear burst order LBO = 0
A1A0 A1A0 A1A0 A1A0
Starting address
First increment
0 0
0 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
Starting Address
First increment
0 0
0 1
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
Second increment 1 0
Third increment 1 1
Second increment 1 0
Third increment 1 1
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AS7C33128NTF18B
®
Synchronous truth table[5,6,7,8,9,11]
Address
CE0 CE1 CE2 ADV/LD R/W
BWn
OE CEN source
CLK
Operation
DQ
High-Z
High-Z
High-Z
High-Z
Q
Notes
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
NA
NA
NA
NA
L to H
L to H
L to H
L to H
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
X
H
X
H
X
H
X
H
CONTINUE DESELECT Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
1
External L to H
Next L to H
X
L
X
L
L
Q
1,10
2
H
H
X
X
X
External L to H NOP/DUMMY READ (Begin Burst) High-Z
X
L
X
L
Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10
External L to H
WRITE CYCLE (Begin Burst)
D
D
3
X
L
X
L
X
L
L
Next L to H WRITE CYCLE (Continue Burst)
1,3,10
H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3
1,2,3,
10
4
X
X
X
H
X
H
X
L
Next L to H WRITE ABORT (Continue Burst)
High-Z
-
X
X
X
X
X
X
X
H
Current L to H
INHIBIT CLOCK
Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb) are HIGH. BWn = L means one or more byte write
signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5 BWa enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins).
6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting CEN HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.
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AS7C33128NTF18B
®
State diagram for NTD SRAM
Burst
Read
Burst
Read
Read
Burst
Read
Dsel
Dsel
Burst
Burst
Burst
Write
Burst
Write
Write
Write
Absolute maximum ratings
Parameter
Symbol
Min
Max
+4.6
+ 0.5
Unit
Power supply voltage relative to GND
V
, V
–0.5
–0.5
–0.5
–
V
DD
DDQ
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
V
V
V
V
IN
IN
DD
V
V
+ 0.5
DDQ
P
1.8
W
D
DC output current
I
–
20
mA
OUT
o
Storage temperature (plastic)
Temperature under bias
T
–65
–65
+150
+135
C
stg
o
T
C
bias
Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
Min
3.135
3.135
0
Nominal
Max
3.465
VDD
0
Unit
V
VDD
3.3
3.3
0
*
VDDQ
V
Vss
V
*
VDDQ cannot be greater than VDD
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
Min
3.135
2.375
0
Nominal
Max
3.465
VDD
0
Unit
V
VDD
3.3
2.5
0
*
VDDQ
V
Vss
V
*
VDDQ cannot be greater than VDD
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AS7C33128NTF18B
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current†
Output leakage current
Sym
Conditions
Min
-2
Max
Unit
µA
|ILI|
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
2
2
|ILO
|
-2
µA
2*
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
VIL
V
V
2*
V
DDQ+0.3
Address and control pins
I/O pins
-0.3**
-0.5**
2.4
0.8
0.8
–
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
V
V
–
0.4
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current†
Output leakage current
Sym
Conditions
Min
-2
Max
Unit
µA
µA
V
|ILI|
VDD = Max, 0V < VIN < VDD
2
2
|ILO
|
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
-2
1.7*
1.7*
-0.3**
-0.3**
1.7
VDD+0.3
Input high (logic 1) voltage
Input low (logic 0) voltage
Output high voltage
VIH
VIL
V
DDQ+0.3
V
Address and control pins
I/O pins
0.7
0.7
–
V
V
IOH = –4 mA, VDDQ = 2.375V
VOH
V
V
I
OH = –1 mA, VDDQ = 2.375V
2.0
–
IOL = 8 mA, VDDQ = 2.625V
–
0.7
0.4
Output low voltage
VOL
I
OL = 1 mA, VDDQ = 2.625V
–
† LBO pin has an internal pull-up and input leakage = -10 µA.
*
V
V
max < VDD +1.5V for pulse width less than 0.2 X t
CYC
IH
**
min = -1.5 for pulse width less than 0.2 X t
CYC
IL
IDD operating conditions and maximum limits
Parameter
Sym
Conditions
-75
-80
-10
Unit
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
,
Operating power supply current1
ICC
260
230
200
mA
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or >
V
– 0.2V, Deselected,
DD
ISB
110
100
90
f = fMax, ZZ < VIL
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Standby power supply current
mA
ISB1
ISB2
30
30
30
30
30
30
Deselected, f = f , ZZ
≥
V
– 0.2V,
Max
DD
all VIN ≤ VIL or ≥ VIH
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
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AS7C33128NTF18B
®
Timing characteristics over operating range
-75
-80
-10
1
Parameter
Sym
Min
8.5
–
Max
–
Min
10
–
Max
–
Min
12
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC
Clock access time
7.5
3.5
–
8.0
4.0
–
10
4.0
–
CD
Output enable low to data valid
Clock high to output low Z
Data Output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Clock high pulse width
–
–
–
OE
2.5
2.5
0
2.5
2.5
0
2.5
2.5
0
2,3,4
2
LZC
OH
–
–
–
–
–
–
2,3,4
2,3,4
2,3,4
5
LZOE
HZOE
HZC
CH
–
–
–
3.5
3.5
–
4.0
4.0
–
4.0
4.0
–
–
–
–
3.0
3.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
0.5
2.0
0.5
4.0
4.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
0.5
2.0
0.5
4.0
4.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
0.5
2.0
0.5
–
–
–
Clock low pulse width
5
CL
–
–
–
Address and Control setup to clock high
Data setup to clock high
6
AS
–
–
–
6
DS
–
–
–
Write setup to clock high
6, 7
6, 8
6
WS
–
–
–
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
CSS
AH
–
–
–
–
–
–
6
DH
–
–
–
Write hold from clock high
Chip select hold from clock high
Clock enable setup to clock high
Clock enable hold from clock high
ADV setup to clock high
6, 7
6, 8
6
WH
–
–
–
CSH
CENS
CENH
ADVS
ADVH
–
–
–
–
–
–
6
–
–
–
6
–
–
–
ADV hold from clock high
6
1 See “Notes:” on page 15.
Snooze Mode Electrical Characteristics
Description
Conditions
ZZ > V
Symbol
Min
Max
Units
mA
Current during Snooze Mode
ZZ active to input ignored
I
30
IH
SB2
PDS
PUS
t
t
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
t
2
ZZI
t
0
RZZI
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AS7C33128NTF18B
®
Key to switching waveforms
don’t care
Undefined
Rising input
Falling input
Timing waveform of read cycle
tCH tCL
tCYC
CLK
tCENS tCENH
CEN
tAS
tAH
A1
A2
A3
Address
R/W
tWS tWH
tCSS tCSH
CE0,CE2
CE1
tADVS
tADVH
ADV/LD
OE
tHZOE
tOE
tLZOE
Q(A2Y‘11)
STALL
Q(A3)
Q(A1)
Q(A2)
Dout
Q(A3Y‘01)
Q(A2Y‘01) Q(A2Y‘10)
BURST
BURST
READ
Q(A2Ý01)
READ
Q(A1)
DSEL
READ
Q(A2)
READ BURST
BURST
Command
READ
Q(A2Ý11)
Q(A3)
READ
Q(A3Ý01)
READ
Q(A2Ý10)
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AS7C33128NTF18B
®
Timing waveform of write cycle
tCH tCL
tCYC
CLK
tCENS tCENH
CEN
tAS
tAH
A1
A2
A3
Address
R/W
BWn
tCSS
tCSH
CE0,CE2
CE1
tADVS
tADVH
ADV/LD
OE
tDS
tDH
D(A3)
D(A1)
D(A2)
Din
tHZOE
D(A2Y‘10)
D(A2Y‘11)
D(A3Y‘01)
D(A2Y‘01)
Dout
Q(n-1)
BURST
WRITE
D(A2Ý10) D(A2Ý11)
BURST
WRITE
BURST
WRITE
D(A2Ý01)
WRITE
D(A1)
DSEL
WRITE
D(A2)
STALL
WRITE
D(A3)
BURST
WRITE
D(A3Ý01)
Command
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AS7C33128NTF18B
®
Timing waveform of read/write cycle
tCH tCL
tCYC
CLK
tCENS
tCENH
CEN
tAS
tAH
A3
A4
A5
A6
A7
A1
A2
ADDRESS
tWS
tWH
R/W
tWH
tWS
BWn
tCSH
tCSS
CE0, CE2
CE1
tADVH
tADVS
ADV/LD
OE
tCD
tLZC
tHZOE
tOE
tDS tDH
tOH
tHZC
D(A5)
Q(A6)
D(A7)
D(A1)
D(A2)
Q(A3)
Q(A4)
Q(A4
Ý
01
)
D(A2Ý01)
D/Q
tLZOE
BURST
WRITE
BURST
READ
READ
Q(A3)
DSEL
WRITE
D(A1)
WRITE
D(A2)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
READ
Q(A4)
Command
D(A2Ý01)
Q(A4Ý01)
Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low.
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P. 12 of 19
AS7C33128NTF18B
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NOP, stall and deselect cycles
CLK
CEN
CE1
CE0, CE2
ADV/LD
R/W
BWn
A1
A2
A3
Address
Q(A1Ý
10)
D(A2)
Q(A1)
Q(A1Ý01)
D/Q
BURST
NOP
D(A2
WRITE
NOP
D(A3)
READ
Q(A1)
STALL
DSEL
BURST
Q(A1 01
BURST
Q(A1 10)
BURST WRITE
DSEL D(A2)
BURST
D(A2Ý10)
Command
Ý
)
Ý
Ý
01
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low.
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P. 13 of 19
AS7C33128NTF18B
®
Timing waveform of snooze mode
CLK
tPUS
ZZ setup cycle
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
Deselect or Read Only
(except ZZ)
Deselect or Read Only
Normal
operation
Cycle
High-Z
Dout
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Alliance Semiconductor
P. 14 of 19
AS7C33128NTF18B
®
AC test conditions
• Output load: For tLZC, tLZOE, tHZOE, and tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 1.0V/ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319
Ω
/1667
Ω
Z0 = 50Ω
50
Ω
DOUT
353 /1538
+3.0V
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
DOUT
5 pF*
90%
10%
GND
Figure A: Input waveform
90%
Ω
Ω
30 pF*
10%
GND
*including scope
and jig capacitance
for 2.5V I/O
Figure B: Output load (A)
Figure C: Output load(B)
Notes:
1) For test conditions, see “AC test conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured high above VIH and tCL measured as low below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/
W
and BW[a,b]
.
8) Chip select refers to CE0
,
CE1, and CE2
.
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Alliance Semiconductor
P. 15 of 19
AS7C33128NTF18B
®
Package dimensions
100-pin quad flat pack (TQFP)
Hd
D
TQFP
Min
A1 0.05
A2 1.35
Max
0.15
b
e
1.45
b
c
0.22
0.09
0.38
0.20
D
E
e
13.90
19.90
14.10
20.10
He
E
0.65 nominal
Hd 15.90
He 21.90
16.10
22.10
0.75
L
L1
a
0.45
1.00 nominal
0° 7°
α
Dimensions in
millimeters
c
L1
L
A1 A2
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AS7C33128NTF18B
®
Ordering information
Package
TQFP
Width
x18
-75
–80
–10
AS7C33128NTF18B-75TQC
AS7C33128NTF18B-75TQI
AS7C33128NTF18B-80TQC
AS7C33128NTF18B-80TQI
AS7C33128NTF18B-10TQC
AS7C33128NTF18B-10TQI
TQFP
x18
Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C33128NTF18B-75TQCN)
Part numbering guide
AS7C
33
128
NTF
18
B
–XX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 128 = 128K
4. NTF = No Turn-Around Delay. Flow-through mode
5. Organization: 18 = x18
6. Production version: B = Product revision
7. Clock access time: [-75 = 7.5 ns; -80 = 8.0 ns; -10 = 10.0]
8. Package type: TQ = TQFP
9. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
10. N = Lead free part
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Alliance Semiconductor
P. 17 of 19
AS7C33128NTF18B
®
Revision History
Rev. No.
History
Revised Date
v 1.0
Initial version
4/28/05
4/28/05, v 1.0
Alliance Semiconductor
P. 18 of 19
AS7C33128NTF18B
®
®
Copyright © Alliance Semiconductor
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
All Rights Reserved
Part Number: AS7C33128NTF18B
Document Version: v 1.0
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective
companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes
no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or
estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The information in this product data
sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the
application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of
Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any
intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from
Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-
supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to
indemnify Alliance against all claims arising from such use.
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