AS7C332MNTD18A [ALSC]
3.3V 2M x 18 Pipelined SRAM with NTD; 3.3V 2M ×18流水线SRAM与NTD
| 型号： | AS7C332MNTD18A |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 2M x 18 Pipelined SRAM with NTD |
| 文件： | 总18页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2004
AS7C332MNTD18A
®
3.3V 2M × 18 Pipelined SRAM with NTDTM
• Byte write enables
Features
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Organization: 2,097,152 words × 18 bits
• NTD™ architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP package
Logic block diagram
21
21
Q
A[20:0]
D
Address
register
Burst logic
CLK
D
Q
CE0
CE1
CE2
Write delay
addr. registers
21
CLK
R/W
BWa
Control
logic
CLK
BWb
ADV / LD
LBO
2 M x 18
SRAM
Array
ZZ
CLK
18
18
DQ[a,b]
Data
Input
Register
D
Q
18
18
CLK
18
CLK
CEN
CLK
Output
Register
OE
18
OE
DQ[a,b]
Selection guide
-200
5
-166
6
-133
7.5
Units
ns
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
200
3.2
450
170
90
166
3.5
400
150
90
133
3.8
MHz
ns
350
140
90
mA
mA
mA
Maximum CMOS standby current (DC)
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Alliance Semiconductor
P. 1 of 18
Copyright © Alliance Semiconductor. All rights reserved.
AS7C332MNTD18A
®
32 Mb Synchronous SRAM products list1,2
Org
Part Number
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
Speed
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
AS7C332MPFS18A
AS7C331MPFS32A
AS7C331MPFS36A
AS7C332MPFD18A
AS7C331MPFD32A
AS7C331MPFD36A
AS7C332MFT18A
AS7C331MFT32A
AS7C331MFT36A
AS7C332MNTD18A
AS7C331MNTD32A
AS7C331MNTD36A
AS7C332MNTF18A
AS7C331MNTF32A
AS7C331MNTF36A
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
FT
7.5/8.5/10 ns
FT
7.5/8.5/10 ns
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
1
TM
NTD -PL
:
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
Flow-through Burst Synchronous SRAM with NTD
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
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P. 2 of 18
AS7C332MNTD18A
®
Pin assignment
100-pin TQFP - top view
1
2
3
4
5
6
7
8
9
NC
NC
NC
A
NC
NC
V
V
NC
DQPa
DQa7
DQa6
V
V
DQa5
DQa4
V
NC
V
ZZ
DQa3
DQa2
V
V
DQa1
DQa0
NC
NC
V
V
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDQ
DDQ
SSQ
SSQ
NC
NC
DQb0
DQb1
V
V
10
11
12
SSQ
SSQ
DDQ
DDQ
DQb2
DQb3
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V
V
DD
DD
SS
TQFP 14 x 20mm
NC
DD
V
SS
DQb4
DQb5
V
V
DDQ
DDQ
SSQ
SSQ
DQb6
DQb7
DQPb
NC
V
V
SSQ
SSQ
DDQ
27
28
29
30
DDQ
NC
NC
NC
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P. 3 of 18
AS7C332MNTD18A
®
Functional description
The AS7C332MNTD18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as
2,097,152 words × 18 bits and incorporates a LATE LATE Write.
This variation of the 32Mb synchronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation
that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for
valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or
read-modify-write operations.
NTD™ devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle
flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With
NTD™, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined
mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W
pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including
burst, can be stalled using the CEN=1, the clock enable input.
The AS7C332MNTD18A operates with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a separate power supply
(VDDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP packages.
TQFP Capacitance
Parameter
Symbol
Test conditions
V = 0V
Min
Max
Unit
pF
*
Input capacitance
I/O capacitance
C
-
-
5
7
IN
in
*
C
V = V = 0V
pF
I/O
in
out
*
Guaranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
θJA
Typical
40
Units
°C/W
°C/W
1–layer
4–layer
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
θJA
22
Thermal resistance
(junction to top of case)1
θJC
8
°C/W
1 This parameter is sampled
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P. 4 of 18
AS7C332MNTD18A
®
Signal descriptions
Signal
CLK
I/O Properties Description
I
I
CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN
SYNC
SYNC
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
A, A0, A1
DQ[a,b]
I
I/O
CE0, CE1,
CE2
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
I
I
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
ADV/LD
R/W
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
SYNC
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
BW[a,b]
OE
I
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
STATIC
LBO
driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
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P. 5 of 18
AS7C332MNTD18A
®
Burst order
Interleaved burst order LBO = 1
A1 A0 A1 A0 A1 A0 A1 A0
Linear burst order LBO = 0
A1 A0 A1 A0 A1 A0 A1 A0
Starting address
First increment
0 0
0 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
Starting Address
First increment
0 0
0 1
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
Second increment 1 0
Third increment 1 1
Second increment 1 0
Third increment
1 1
Synchronous truth table[5,6,7,8,9,11]
Address
CE0 CE1 CE2 ADV/LD R/W
BWn
OE CEN source
CLK
Operation
DQ
High-Z
High-Z
High-Z
High-Z
Q
Notes
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
NA
NA
NA
NA
L to H
L to H
L to H
L to H
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
X
H
X
H
X
H
X
H
CONTINUE DESELECT Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
1
External L to H
Next L to H
X
L
X
L
L
Q
1,10
2
H
H
X
X
X
External L to H NOP/DUMMY READ (Begin Burst) High-Z
X
L
X
L
Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10
External L to H
WRITE CYCLE (Begin Burst)
D
D
3
X
L
X
L
X
L
L
Next L to H WRITE CYCLE (Continue Burst)
1,3,10
H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3
1,2,3,
X
X
X
H
X
H
X
X
L
Next L to H WRITE ABORT (Continue Burst)
High-Z
10
X
X
X
X
X
X
H
Current L to H
INHIBIT CLOCK
-
4
Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa and BWb) are HIGH. BWn = L means one or more byte write
signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the ini-
tial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5 BWa enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins).
6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting CEN HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low in this truth table.
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P. 6 of 18
AS7C332MNTD18A
®
State diagram for NTD SRAM
Burst
Read
Burst
Read
Read
Burst
Read
Dsel
Dsel
Burst
Burst
Write
Burst
Write
Burst
Write
Write
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
Symbol
Min
Max
+4.6
Unit
V
VDD, VDDQ
VIN
–0.5
–0.5
–0.5
–
VDD + 0.5
VDDQ + 0.5
1.8
V
VIN
V
Pd
W
Short circuit output current
IOUT
Tstg
–
20
mA
oC
oC
Storage temperature
–65
–65
+150
Temperature under bias
Tbias
+135
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
3.135
0
Nominal
Max
3.465
3.465
0
Unit
V
3.3
3.3
0
VDDQ
Vss
V
V
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
Min
3.135
2.375
0
Nominal
Max
3.465
2.625
0
Unit
V
VDD
VDDQ
Vss
3.3
2.5
0
V
V
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P. 7 of 18
AS7C332MNTD18A
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current†
Output leakage current
Sym
|ILI|
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
2
|ILO
|
-2
2*
2*
-0.3**
-0.5**
2.4
–
2
VDD+0.3
VDDQ+0.3
0.8
µA
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
V
V
Address and control pins
I/O pins
VIL
0.8
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
–
V
V
0.4
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current†
Output leakage current
Sym
|ILI|
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
2
µA
µA
V
|ILO
|
-2
2
VDD+0.3
VDDQ+0.3
0.7
1.7*
1.7*
-0.3**
-0.3**
1.7
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
V
Address and control pins
I/O pins
V
VIL
0.7
V
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
–
V
–
0.7
V
† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**
V
min = -1.5 for pulse width less than 0.2 X tCYC
IL
IDD operating conditions and maximum limits
Parameter
Sym
Test conditions
-200
-166
-133
Unit
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
,
Operating power supply
current
I
450
400
150
350
mA
1
CC
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or >
V
– 0.2V, Deselected,
DD
I
170
140
SB
f = fMax, ZZ < VIL
Standby power supply
current
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
mA
I
I
90
80
90
80
90
80
SB1
SB2
Deselected, f = f , ZZ
≥
V
– 0.2V,
DD
Max
all VIN ≤ VIL or ≥ VIH
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
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AS7C332MNTD18A
®
Timing characteristics over operating range
-200
-166
-133
1
Parameter
Sym
Unit Notes
Min
Max
200
–
Min
Max
166
–
Min
Max
Clock frequency
F
t
–
–
6
–
133 MHz
MAX
CYC
Cycle time
5
7.5
–
–
3.8
3.8
–
ns
ns
Clock access time
t
–
3.2
3.2
–
–
3.5
3.5
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
–
ns
OE
t
0
0
0
ns
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
1.5
0
–
ns
OH
t
–
–
–
ns
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.0
3.0
–
–
3.4
3.4
–
–
3.8
3.8
–
ns
t
–
–
–
ns
HZC
t
0
0
0
ns
OHOE
t
2.0
2.0
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
0.4
1.4
0.4
2
–
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
2
–
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
2
–
ns
5
5
CH
Clock low pulse width
t
t
t
–
–
–
ns
CL
AS
DS
Address and Control setup to clock high
Data setup to clock high
–
–
–
ns
6
–
–
–
ns
6
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
Clock enable setup to clock high
Clock enable hold from clock high
ADV setup to clock high
ADV hold from clock high
ZZ High to Power down
t
–
–
–
ns
6, 7
6, 8
6
WS
t
–
–
–
ns
CSS
t
–
–
–
ns
AH
DH
WH
t
–
–
–
ns
6
t
–
–
–
ns
6, 7
6, 8
6
t
–
–
–
ns
CSH
t
–
–
–
ns
CENS
CENH
ADVS
t
t
–
–
–
ns
6
–
–
–
ns
6
t
–
–
–
ns
6
ADVH
tPDS
–
–
–
cycle
cycle
ZZ Low to Power up
tPUS
2
–
2
–
2
–
1 See “Notes” on page 15
Snooze Mode Electrical Characteristics
Description
Conditions
ZZ > V
Symbol
Min
Max
Units
mA
Current during Snooze Mode
ZZ active to input ignored
I
80
IH
SB2
PDS
PUS
t
t
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
t
2
ZZI
t
0
RZZI
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AS7C332MNTD18A
®
Key to switching waveforms
don’t care
Undefined
Rising input
Falling input
Timing waveform of read cycle
tCH tCL
tCYC
CLK
tCES tCEH
CEN
tAS
tAH
A1
tWS tWH
A2
A3
Address
R/W
tWS tWH
BWn
tCSH
CE0,CE2
CE1
tADVS
tADVH
ADV/LD
OE
tHZOE
tOE
tHLZC
tLZOE
Q(A2Y‘10)
Q(A3)
Q(A1)
Q(A2)
Dout
Q(A2Y‘11)
Q(A2Y‘01)
Continue
Read
Read
Q(A2)
Continue
Read
Q(A2Y‘10)
Read
Q(A1)
Continue
Read
Q(A2Y‘01)
Continue
Read
Q(A2Y‘11)
Inhibit
Clock
DSEL
Read
Q(A3)
Q(A3Y‘01)
12/23/04, V 1.6
Alliance Semiconductor
P. 10 of 18
AS7C332MNTD18A
®
Timing waveform of write cycle
tCH tCL
tCYC
CLK
tCES tCEH
CEN
tAS
tAH
A1
A2
A3
Address
R/W
BWn
tCSH
CE0,CE2
CE1
tADVS
tADVH
ADV/LD
OE
tDS
tDH
D(A3)
D(A1)
D(A2)
Din
tHZOE
D(A2Y‘10) D(A2Y‘11)
D(A2Y‘01)
Dout
Q(n-2)
Q(n-1)
Continue
Write
D(A3Y‘01)
Write
D(A2)
Continue
Write
D(A2Y‘10)
Write
D(A1)
Continue
Write
D(A2Y‘01)
Continue
Write
D(A2Y‘11)
Inhibit
Clock
Write
D(A3)
DSEL
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Alliance Semiconductor
P. 11 of 18
AS7C332MNTD18A
®
Timing waveform of read/write cycle
tCH tCL
tCYC
CLK
tCENS
tCENH
CEN
CE1
tCSS
tCSH
CE0, CE2
tADVS
tADVH
ADV/LD
R/W
tWS
tWH
tWS
tWH
BWn
tAS
tAH
A7
A3
A4
A5
A6
A1
A2
ADDRESS
tCD
tLZC
tDS tDH
tOH
tOE
tHZC
D(A5)
Q(A6)
D/Q
OE
D(A1)
D(A2)
Q(A3)
Q(A4)
Q(A4
Ý
01)
D(A2Ý01)
tHZOE
tLZOE
Burst
Write
D(A2Ý01)
Write
D(A1)
Burst
Read
Q(A4Ý01)
Read
Q(A3)
DSEL
Write
D(A2)
Write
D(A5)
Read
Q(A6)
Write
D(A7)
Read
Q(A4)
Command
Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care.
12/23/04, V 1.6
Alliance Semiconductor
P. 12 of 18
AS7C332MNTD18A
®
NOP, stall and deselect cycles
CLK
CEN
CE1
CE0, CE2
ADV/LD
R/W
BWn
A1
A2
A3
Address
Q(A1Ý01)
Q(A1Ý
10)
D(A2)
Q(A1)
D/Q
Burst
NOP
D(A2Ý01
Write
NOP
D(A3)
Read
Q(A1)
STALL
DSEL
Burst
Q(A1Ý01
Command
Burst
Q(A1Ý10)
Burst
DSEL
Write
D(A2)
Burst
D(A2Ý10)
)
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low.
12/23/04, V 1.6
Alliance Semiconductor
P. 13 of 18
AS7C332MNTD18A
®
Timing waveform of snooze mode
CLK
tPUS
ZZ setup cycle
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
Deselect or Read Only
(except ZZ)
Deselect or Read Only
Normal
operation
Cycle
High-Z
Dout
12/23/04, V 1.6
Alliance Semiconductor
P. 14 of 18
AS7C332MNTD18A
®
AC test conditions
• Output load: For tLZC, tLZOE, tHZOE, and tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω/1667Ω
50
Ω
DOUT
353 /1538
7
Ω
+
3.0V
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
DOUT
5 pF*
GND
90%
10%
GND
Figure A: Input waveform
90%
Ω
Ω
30 pF*
10%
*including scope
and jig capacitance
for 2.5V I/O
Figure B: Output load (A)
Figure C: Output load(B)
Notes
1) For test conditions, see “AC test conditions”, Figures A, B, and C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
5) tCH is measured high above VIH, and tCL is measured low below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/
W
and BW[a,b]
.
8) Chip select refers to CE0
,
CE1, and CE2.
12/23/04, V 1.6
Alliance Semiconductor
P. 15 of 18
AS7C332MNTD18A
®
Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Hd
D
Min
0.05
1.35
0.22
0.09
Max
0.15
1.45
0.38
0.20
A1
A2
b
b
e
c
D
13.90 14.10
19.90 20.10
0.65 nominal
15.90 16.10
21.90 22.10
He
E
E
e
Hd
He
L
0.45
1.00 nominal
0° 7°
0.75
L1
α
α
Dimensions in millimeters
c
L1
L
A1 A2
12/23/04, V 1.6
Alliance Semiconductor
P. 16 of 18
AS7C332MNTD18A
®
Ordering information
Package & Width
–200
–166
–133
AS7C332MNTD18A-200TQC
AS7C332MNTD18A-200TQI
AS7C332MNTD18A-166TQC
AS7C332MNTD18A-166TQI
AS7C332MNTD18A-133TQC
AS7C332MNTD18A-133TQI
TQFP x 18
Note:
Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C332MNTD18A-200TQCN)
Part numbering guide
AS7C
33
2M
NTD
18
A
–XXX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 2M = 2Meg
4. NTD™ = No Turn-Around Delay. Pipelined mode
5. Organization: 18 = x 18
6. Production version: A = first production version
7. Clock speed (MHz)
8. Package type: TQ = TQFP
9. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
10. N = Lead Free Part
12/23/04, V 1.6
Alliance Semiconductor
P. 17 of 18
AS7C332MNTD18A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C332MNTD18A
Document Version: V 1.6
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The
information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
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or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including
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