AS7C33512NTD18A [ALSC]
3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD; 3.3V 512K ×18的流水线突发同步SRAM与NTD
| 型号： | AS7C33512NTD18A |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| 文件： | 总19页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2004
AS7C33512NTD18A
®
3.3V 512K × 18 Pipelined burst Synchronous SRAM with NTDTM
Features
• Byte write enables
• Organization: 524,288 words × 18 bits
• NTD™ architecture for efficient bus operation
• Fast clock speeds to 166 MHz
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed WRITE cycles
• Fully synchronous operation
• “Interleaved” or “Linear burst” modes
• Snooze mode for standby operation
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in100-pin TQFP
Logic block diagram
19
19
Address Q
D
A[18:0]
register
Burst logic
CLK
D
Q
Write delay
addr. registers
CLK
CE0
CE1
CE2
19
R/W
BWa
BWb
Control
logic
CLK
ADV/LD
LBO
512K x 18
SRAM
Array
ZZ
CLK
18
18
Data
DQ [a:b]
Q
D
Input
Register
18
18
CLK
18
CLK
CLK
CEN
Output
Register
OE
18
OE
DQ[a:b]
Selection Guide
-166
6
–133
7.5
133
4
Units
ns
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
166
3.5
475
130
30
MHz
ns
400
100
30
mA
mA
mA
Maximum CMOS standby current (DC)
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512NTD18A
®
1,2
8 Mb Synchronous SRAM products list
Org
Part Number
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
Speed
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
AS7C33512PFS18A
AS7C33256PFS32A
AS7C33256PFS36A
AS7C33512PFD18A
AS7C33256PFD32A
AS7C33256PFD36A
AS7C33512FT18A
AS7C33256FT32A
AS7C33256FT36A
AS7C33512NTD18A
AS7C33256NTD32A
AS7C33256NTD36A
AS7C33512NTF18A
AS7C33256NTF32A
AS7C33256NTF36A
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
1
TM
NTD -PL
:
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
Flow-through Burst Synchronous SRAM with NTD
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
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AS7C33512NTD18A
®
Pin arrangement for TQFP
A
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
2
NC
NC
3
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
5
6
DQpa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
NC
7
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
8
9
10
11
12
13
NC 14
TQFP 14 × 20mm
NC
VDD
ZZ
VDD
15
NC 16
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQpb
17
18
19
20
21
22
23
24
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
NC
NC
NC 25
VSSQ
VDDQ
NC 28
NC 29
NC 30
VSSQ
VDDQ
NC
26
27
NC
NC
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AS7C33512NTD18A
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Functional description
The AS7C33512NTD18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM)
organized as 524,288 words × 18 bits and incorporates a LATE LATE Write.
™
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD ) architecture, featuring an enhanced
write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce
overall bandwidth for applications requiring random access or read-modify-write operations.
™
NTD devices use the memory bus more efficiently by introducing a write 'latency' which matches the two cycle pipeline and
one cycle flowthrough read latency. Write data is applied two cycles after the write command and address, allowing the read
™
pipeline to clear. With NTD , write and read operations can be used in any order without producing dead bus cycles.
Assert R/W LOW to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied LOW for
full 18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is
applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled
for write operations; it can be tied LOW for normal operations. Outputs go to a high impedance state when the device is de-
selected by any of the three chip enable inputs (refer to synchronous truth table on page page 6.) In pipeline mode, a two cycle
deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is HIGH, external
addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the
LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD18A operate with a 3.3V ± 5% power supply for the device core (V ). DQ circuits use a separate
DD
power supply (V
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP.
DDQ
Capacitance
Parameter
Symbol
Signals
Address and control pins
I/O pins
Test conditions
= 0V
Max
Unit
pF
*
Input capacitance
I/O capacitance
C
V
5
7
IN
IN
*
C
V
= V = 0V
OUT
pF
I/O
IN
*
Guaranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
θJA
Typical
Units
1–layer
4–layer
40
22
°C/W
°C/W
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
θJA
Thermal resistance
(junction to top of case)1
θJC
8
°C/W
1 This parameter is sampled
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AS7C33512NTD18A
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Signal descriptions
Signal
I/O Properties
Description
CLK
I
I
CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN
SYNC
SYNC
SYNC
Clock enable. When de-asserted HIGH, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
A, A0, A1
DQ[a,b]
I
I/O
CE0, CE1,
CE2
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is HIGH.
I
I
I
SYNC
Advance or Load. When sampled HIGH, the internal burst address counter will increment
in the order defined by the LBO input value. (refer to table on page 2) When LOW, a new
address is loaded.
ADV/LD
R/W
SYNC
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a
WRITE operation. Is ignored when ADV/LD is HIGH.
SYNC
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
BW[a,b]
OE
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to V or left floating, device follows Interleaved Burst
DD
LBO
I
STATIC order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
ZZ
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.
NC
-
No connects. Note that pin 84 will be used for future address expansion to 18Mb density.
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I . The
SB2
duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
is guaranteed after the time t
is met. After entering SNOOZE MODE, all
SB2
ZZI
inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not
guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid
pending operations are completed. Similarly, when exiting SNOOZE MODE during t , only a DESELECT or READ cycle
PUS
should be given while the SRAM is transitioning out of SNOOZE MODE.
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AS7C33512NTD18A
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Burst Order
Interleaved burst order (LBO = 1)
A1 A0 A1 A0 A1 A0 A1 A0
Linear burst order (LBO = 0)
A1 A0 A1 A0 A1 A0 A1 A0
0 0 0 1 1 0 1 1
0 1 1 0 1 1 0 0
Starting address
First increment
0 0
0 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
Starting Address
First increment
Second increment 1 0
Third increment 1 1
Second increment 1 0
1 1
0 0
0 0
0 1
0 1
1 0
Third increment
1 1
[5,6,7,8,9,11]
Synchronous truth table
Address
CE0 CE1 CE2 ADV/LD R/W
BWn
X
OE CEN source
CLK
Operation
DQ
High-Z
High-Z
High-Z
High-Z
Q
Notes
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
NA
NA
NA
NA
L to H
L to H
L to H
L to H
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
X
X
X
H
X
H
X
H
X
H
X
CONTINUE DESELECT Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
1
X
External L to H
Next L to H
X
L
X
L
X
L
Q
1,10
2
X
H
H
X
X
X
External L to H NOP/DUMMY READ (Begin Burst) High-Z
X
L
X
L
X
Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10
L
External L to H
WRITE CYCLE (Begin Burst)
D
D
3
X
L
X
L
X
L
L
Next L to H WRITE CYCLE (Continue Burst)
1,3,10
H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3
1,2,3,
10
4
X
X
X
X
X
X
H
X
X
X
H
X
X
X
L
Next L to H WRITE ABORT (Continue Burst)
High-Z
-
H
Current L to H
INHIBIT CLOCK
Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa and BWb) are HIGH. BWn = L means one or more byte write
signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the ini-
tial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5 BWa enables WRITEs to byte “a” (DQa pins/balls); BWb enables WRITEs to byte “b” (DQb pins/balls).
6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting CEN HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low in this truth table.
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AS7C33512NTD18A
®
State Diagram for NTD SRAM
Burst
Read
Burst
Read
Read
Burst
Read
Dsel
Dsel
Burst
Burst
Burst
Write
Write
Write
Burst
Write
1
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
Symbol
Min
Max
Unit
V
V
, V
–0.5
–0.5
–0.5
–
+4.6
DD
DDQ
V
V
+ 0.5
DD
V
IN
IN
V
V
+ 0.5
V
DDQ
P
1.8
W
D
DC output current
I
–
50
mA
°C
°C
OUT
Storage temperature (plastic)
Temperature under bias
T
–65
–65
+150
+135
stg
T
bias
1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
3.135
0
Nominal
Max
3.465
3.465
0
Unit
V
3.3
3.3
0
VDDQ
Vss
V
V
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
2.375
0
Nominal
Max
3.465
2.625
0
Unit
V
3.3
2.5
0
VDDQ
Vss
V
V
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AS7C33512NTD18A
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DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current1
Output leakage current
Sym
|ILI|
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
2
|ILO
|
-2
2*
2*
-0.3**
-0.5**
2.4
–
2
VDD+0.3
VDDQ+0.3
0.8
µA
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
V
V
Address and control pins
I/O pins
VIL
0.8
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
–
V
V
0.4
1 LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current
Output leakage current
Sym
|ILI|
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
2
µA
µA
V
|ILO
|
-2
2
VDD+0.3
VDDQ+0.3
0.7
1.7*
1.7*
-0.3**
-0.3**
1.7
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
V
Address and control pins
I/O pins
V
VIL
0.7
V
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
–
V
–
0.7
V
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**
V
min = -1.5 for pulse width less than 0.2 X tCYC
IL
I
operating conditions and maximum limits
DD
Parameter
Sym
Test conditions
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
IOUT = 0 mA, ZZ < VIL
-166
-133
Unit
,
Operating power supply
I
475
400
mA
1
CC
current
All VIN ≤ 0.2V or >
V
– 0.2V, Deselected,
DD
I
130
100
SB
f = fMax, ZZ < VIL
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Standby power supply current
mA
I
I
30
30
30
30
SB1
SB2
Deselected, f = f , ZZ
≥
V
– 0.2V,
Max
DD
all VIN ≤ VIL or ≥ VIH
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
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Timing characteristics over operating range for 3.3V I/O
–166
–133
1
Parameter
Symbol
Unit
MHz
ns
Notes
Min
Max
166
–
Min
Max
133
–
Clock frequency
Cycle time
f
–
–
Max
t
6
7.5
–
CYC
Clock access time
t
–
3.5
3.5
–
4.0
4.0
–
ns
CD
Output enable LOW to data valid
Clock HIGH to output Low Z
Data output invalid from clock HIGH
Output enable LOW to output Low Z
Output enable HIGH to output High Z
Clock HIGH to output High Z
Output enable HIGH to invalid output
Clock HIGH pulse width
t
–
–
ns
OE
t
0
0
ns
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
ns
OH
t
–
–
ns
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
–
4.0
4.0
–
ns
ns
ns
t
–
–
HZC
t
0
0
OHOE
t
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
–
ns
5
5
CH
Clock LOW pulse width
t
t
t
–
–
ns
CL
AS
DS
Address setup to clock HIGH
Data setup to clock HIGH
–
–
ns
6
–
–
ns
6
Write setup to clock HIGH
t
–
–
ns
6,7
6,8
6
WS
Chip select setup to clock HIGH
Address hold from clock HIGH
Data hold from clock HIGH
t
–
–
ns
CSS
t
–
–
ns
AH
DH
WH
t
–
–
ns
6
Write hold from clock HIGH
Chip select hold from clock HIGH
Clock enable setup to clock HIGH
Clock enable hold from clock HIGH
ADV/LD setup to clock HIGH
ADV/LD hold from clock HIGH
1 Refer to “notes” on page 16.
t
–
–
ns
6,7
6,8
6
t
–
–
ns
CSH
t
–
–
ns
CENS
CENH
ADVS
ADVH
t
t
–
–
ns
6
–
–
ns
6
t
–
–
ns
6
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Timing characteristics over operating range for 2.5 V I/O
–166
–133
1
Parameter
Symbol
Min Max Min Max Unit Notes
Clock frequency
Cycle time
f
–
166
–
–
133 MHz
Max
t
6
7.5
–
–
4.5
4.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYC
Clock access time
t
–
4.0
3.5
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output High Z
Clock high to output High Z
Output enable high to invalid output
Clock high pulse width
t
–
–
OE
t
0
0
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
OH
t
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
–
4.0
4.0
–
t
–
–
HZC
t
0
0
OHOE
t
2.4
2.3
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
0.7
1.7
0.7
–
2.5
2.5
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
0.7
1.7
0.7
–
5
5
CH
Clock low pulse width
t
t
t
–
–
CL
AS
DS
Address setup to clock high
Data setup to clock high
–
–
6
–
–
6
Write setup to clock high
t
–
–
6,7
6,8
6
WS
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
t
–
–
CSS
t
–
–
AH
DH
WH
t
–
–
6
Write hold from clock high
Chip select hold from clock high
Clock enable setup to clock high
Clock enable hold from clock high
ADV/LD setup to clock high
ADV/LD hold from clock high
1 Refer to “notes” onpage 16.
t
–
–
6,7
6,8
6
t
–
–
CSH
t
–
–
CENS
CENH
ADVS
ADVH
t
t
–
–
6
–
–
6
t
–
–
6
Snooze Mode Electrical Characteristics
Description
Conditions
ZZ > V
Symbol
Min
Max
Units
Current during Snooze Mode
ZZ active to input ignored
I
30
mA
IH
SB2
PDS
PUS
t
t
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
t
2
ZZI
t
0
RZZI
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Key to switching waveforms
don’t care
Undefined
Rising input
Falling input
Timing waveform of read cycle
tCH tCL
tCYC
CLK
tCEH
tCES
CEN
tAS
tAH
A1
tWS tWH
A2
A3
Address
R/W
tWS tWH
BWn
tCSH
CE0,CE2
CE1
tADVS
tADVH
ADV/LD
OE
tHZOE
tOE
tHLZC
tLZOE
Q(A2Y‘10)
Q(A3)
Q(A1)
Q(A2)
Dout
Q(A2Y‘11)
Q(A2Y‘01)
Continue
Read
Read
Q(A2)
Continue
Read
Q(A2Y‘10)
Read
Q(A1)
Continue
Read
Q(A2Y‘01)
Continue
Read
Q(A2Y‘11)
Inhibit
Clock
DSEL
Read
Q(A3)
Q(A3Y‘01)
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Timing waveform of write cycle
tCH tCL
tCYC
CLK
tCES tCEH
CEN
tAS
tAH
A1
A2
A3
Address
R/W
BWn
tCSH
CE0,CE2
CE1
tADVS
tADVH
ADV/LD
OE
tDS
tDH
D(A3)
D(A1)
D(A2)
Din
tHZOE
D(A2Y‘10) D(A2Y‘11)
D(A2Y‘01)
Dout
Q(n-2)
Q(n-1)
Continue
Write
D(A3Y‘01)
Write
D(A2)
Continue
Write
D(A2Y‘10)
Write
D(A1)
Continue
Write
D(A2Y‘01)
Continue
Write
D(A2Y‘11)
Inhibit
Clock
Write
D(A3)
DSEL
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Timing waveform of read/write cycle
tCH tCL
tCYC
CLK
tCENS
tCENH
CEN
CE1
tCSS
tCSH
CE0, CE2
tADVS
tADVH
ADV/LD
R/W
tWS
tWH
tWS
tWH
BWn
tAS
tAH
A7
A3
A4
A5
A6
A1
A2
ADDRESS
tCD
tLZC
tDS tDH
tOH
tOE
tHZC
D(A5)
Q(A6)
D/Q
OE
D(A1)
D(A2)
Q(A3)
Q(A4)
Q(A4
Ý
01)
D(A2Ý01)
tHZOE
tLZOE
Burst
Write
D(A2Ý01)
Write
D(A1)
Burst
Read
Q(A4Ý01)
Read
Q(A3)
DSEL
Write
D(A2)
Write
D(A5)
Read
Q(A6)
Write
D(A7)
Read
Q(A4)
Command
Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care.
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NOP, stall and deselect cycles
CLK
CEN
CE1
CE0, CE2
ADV/LD
R/W
BWn
A1
A2
A3
Address
Q(A1Ý01)
Q(A1Ý
10)
D(A2)
Q(A1)
D/Q
Burst
NOP
D(A2Ý01
Write
NOP
D(A3)
Read
Q(A1)
STALL
DSEL
Burst
Q(A1Ý01
Command
Burst
Q(A1Ý10)
Burst
DSEL
Write
D(A2)
Burst
D(A2Ý10)
)
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low.
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Timing waveform of snooze mode
CLK
tPUS
ZZ setup cycle
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
Deselect or Read Only
(except ZZ)
Deselect or Read Only
Normal
operation
Cycle
High-Z
Dout
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AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω/1667Ω
Z0 = 50Ω
50
Ω
DOUT
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
+3.0V
DOUT
90%
10%
90%
10%
5 pF*
353Ω/1538Ω
30 pF*
GND
*including scope
and jig capacitance
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This paracmeter measured with output load conditon in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured HIGH above VIH and tCL measured as LOW below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/
W,
BW[a:b]
.
8) Chip select refers to CE0
,
CE1, CE2.
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Package Dimensions :100-pin quad flat pack (TQFP)
Hd
Hd
D
TQFP
Min
0.05
Max
0.15
A1
A2
b
b
e
1.35
1.45
0.22
0.38
α
0.09
0.20
c
13.90
19.90
14.10
20.10
D
E
He
E
0.65 nominal
e
15.90
21.90
0.45
16.10
22.10
0.75
Hd
He
L
L1
α
c
L1
L
A1 A2
1.00 nominal
0°
7°
Dimensions in millimeters
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Ordering information
Package &Width
TQFP x18
–166
–133
AS7C33512NTD18A-166TQC
AS7C33512NTD18A-166TQI
AS7C33512NTD18A-133TQC
AS7C33512NTD18A-133TQI
TQFP x18
Notes: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C33512NTD18A-166TQCN)
Part numbering guide
AS7C
33
512
NTD
18
A
–XXX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33=3.3V
3. Organization: 512=512K
4. NTD™ = No-Turn Around Delay. Pipelined mode.
5. Organization: 18=x18
6. Production version: A=first production version
7. Clock speed (MHz)
8. Package type: TQ=TQFP
9. Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
10. N = Lead free part
11/30/04; v.2.1
Alliance Semiconductor
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AS7C33512NTD18A
®
®
Alliance
Corporation
Semiconductor
Copyright © Alliance Semiconductor
All Rights Reserved
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
Part Number: AS7C33512NTD18A
Document Version: v.2.1
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
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相关型号：
AS7C33512NTD18A-100TQIN
ZBT SRAM, 512KX18, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100
ALSC
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