AS7C33512PFD32A-200TQC [ALSC]
Standard SRAM, 512KX32, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100;
| 型号： | AS7C33512PFD32A-200TQC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 512KX32, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 静态存储器 |
| 文件： | 总2页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2001
Advanced Information
AS7C33512PFD32A
AS7C33512PFD36A
®
3.3V 512K × 32/ 36 pipeline burst synchronous SRAM
Features
• 100-pin TQFP package
• Organization: 524,288 words x 32/ 36 bits
• Fast clock speeds to 200MHz in LVTTL/ LVCMOS
• Fast clock to data access: 3.0/ 3.5/ 4.0 ns
• Fast OEaccess time: 3.0/ 3.5/ 4.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Dual-cycle deselect
• 119-Ball BGA (7 x 17 Ball Grid Array Package)
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/ O operation with separate V
DDQ
*
• NTD™ pipeline architecture available
(AS7C33512NTD32A/ AS7C33512NTD36A)
- Single-cycle deselect also available ( AS7C33512PFS32A/
AS7C33512PFS36A)
• Pentium® compatible architecture and timing
Logic Block Diagram:
*
®
* Pentium is a registered trademark of Intel Corporation. NTD™ is a
• Asynchronous output enable control
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Pin Arrangements:
CLK
ADV
ADSC
ADSP
CLK
CE
CLR
Burst logic
512K × 32/ 36
Memory
DQP / NC
b
DQP / NC
c
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
18
16
18
19
array
DQ
b
DQ
c
2
D
CE
CLK
Q
A[18:0]
DQ
DQ
3
Address
b
DDQ
c
V
register
V
4
DDQ
V
V
5
SSQ
SSQ
DQ
6
DQ
b
c
36/ 32
36/ 32
DQ
b
DQ
c
7
GWE
BWE
BW
d
D
Q
Q
Q
Q
DQ
d
Byte write
DQ
b
DQ
c
8
DQ
DQ
c
9
b
registers
CLK
V
10
11
12
13
V
V
SSQ
SSQ
V
DDQ
DDQ
DQ
DQ
c
b
D
DQ
c
DQ
b
DQ
c
BW
c
Byte write
FT 14
V
SS
registers
V
15
NC
VDD
ZZ
DD
CLK
D
TQFP 14 × 20 mm
512K x 32A/ 36A
NC 16
V
17
18
19
20
21
22
23
24
25
26
27
28
29
SS
DQ
b
DQ
DQ
DQ
BW
a
d
d
b
Byte write
DQ
a
registers
V
V
V
DDQ
DDQ
CLK
V
SSQ
SSQ
D
DQ
DQ
a
d
d
d
d
DQ
a
4
DQ
a
DQ
DQ
DQ
V
BW
a
Byte write
DQ
a
registers
DQ
CLK
D
a
V
V
SSQ
SSQ
CE0
CE1
CE2
V
DDQ
DDQ
OE
Output
registers
CLK
Q
Q
DQ
DQ
a
d
Input
registers
CLK
Enable
register
DQ
a
DQ
d
CE
CLK
DQP / NC
a
DQP / NC 30
d
D
Enable
delay
Power
down
ZZ
register
CLK
Note: Pins 1,30,51,80 are NC for ×32
OE
DATA [35:0]
DATA [31:0]
FT
Selection guide
Minimum cycle time
-200
-166
6
-100
10
Units
5
ns
MHz
ns
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
200
3.0
400
110
30
166
3.5
350
110
30
100
4.0
250
70
mA
mA
mA
Maximum CMOS standby current (DC)
30
8/ 27/ 01; v.0.9.1
Alliance Semiconductor
1 of 2
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512PFD32A
AS7C33512PFD36A
®
Pin Configuration
119 BGA Top View
1
2
3
4
5
6
7
ADSP
ADSC
A
B
C
D
E
F
V
A
A
A
A
A
A
A
A
A
A
A
A
V
DDQ
DDQ
NC
NC
FT
V
NC
DD
DQC DQPc
V
NC
CE0
V
DQpb DQb
SS
SS
DQC
DQc
DQc
DQc
DQc
V
V
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
SS
SS
OE
V
V
V
V
DDQ
DDQ
SS
BWc
SS
BWb
ADV
GWE
G
H
J
DQC
DQC
DQb
DQb
V
V
SS
SS
V
V
NC
V
NC
VSS
BWa
V
DDQ
DDQ
DD
DD
K
L
M
N
P
DQd
DQd
DQd
DQd
DQd
DQd
V
CLK
NC
BWE
A1
DQa
DQa
SS
BWd
V
V
V
V
DDQ
DDQ
SS
SS
DQd
V
V
DQa
SS
SS
DQd DQpd
V
A0
V
DQa
NC
ZZ
SS
SS
R
T
U
NC
NC
A
LBO
A
V
V
DD
DD
NC
A
A
NC
V
TMS
TDI
TCK
TDO
NC
V
DDQ
DDQ
Note: For P/ N AS7C512PFD32A, 4 of the I/ O Pins must be left open (N.C.)
8/ 27/ 01; v.0.9.1
Alliance Semiconductor
2 of 2
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