AS7C33512PFS18A [ALSC]
3.3V 512K x 18 pipeline burst synchronous SRAM; 3.3V 512K ×18管道爆裂的同步SRAM
| 型号： | AS7C33512PFS18A |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| 文件： | 总20页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2004
AS7C33512PFS18A
®
3.3V 512K × 18 pipeline burst synchronous SRAM
Features
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• 30 mW typical standby power in power down mode
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Organization: 524,288 words × 18 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Single-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
DDQ
Logic block diagram
LBO
Burst logic
CLK
ADV
CLK
CS
CLR
ADSC
ADSP
512K × 18
Memory
array
19 17
19
19
Q
D
A[18:0]
Address
register
CS
CLK
18
18
2
GWE
BWb
D
Q
DQb
Byte Write
registers
BWE
BWa
CLK
D
Q
DQa
Byte Write
registers
CLK
CE0
CE1
OE
Output
D
Q
Q
Input
registers
Enable
register
CE
CLK
CE2
registers
CLK
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
OE
18
DQ[a,b]
Selection guide
–166
6
–133
7.5
133
4
Units
ns
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
166
3.5
475
130
30
MHz
ns
425
100
30
mA
mA
mA
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Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512PFS18A
®
1,2
8 Mb Synchronous SRAM products list
Org
Part Number
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
Speed
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
AS7C33512PFS18A
AS7C33256PFS32A
AS7C33256PFS36A
AS7C33512PFD18A
AS7C33256PFD32A
AS7C33256PFD36A
AS7C33512FT18A
AS7C33256FT32A
AS7C33256FT36A
AS7C33512NTD18A
AS7C33256NTD32A
AS7C33256NTD36A
AS7C33512NTF18A
AS7C33256NTF32A
AS7C33256NTF36A
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
1
TM
NTD -PL
:
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
Flow-through Burst Synchronous SRAM with NTD
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the prop-
erty of their respective owners.
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AS7C33512PFS18A
®
Pin arrangement
A
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
2
NC
NC
3
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
5
6
DQpa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
NC
NC
7
DQb0
DQb1
VSSQ
VDDQ
8
9
10
11
DQb2 12
DQb3 13
NC 14
TQFP 14 × 20mm
VDD
15
VDD
ZZ
NC 16
VSS 17
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
NC
DQb4 18
DQb5 19
VDDQ
VSSQ
20
21
DQb6 22
DQb7 23
DQpb 24
NC 25
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
26
27
NC 28
NC 29
NC 30
NC
NC
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AS7C33512PFS18A
®
Functional description
The AS7C33512PFS18A is a high performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) device organized as
524,288 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP,
and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 6/7.5 ns with clock access times (tCD) of 3.5/4.0 ns enable 166 and 133 MHz bus frequencies. Three chip enable inputs
permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor
address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and
driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on
all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address
strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium®
count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW. This device operates in single-cycle deselect feature during
read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
•
•
ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC
WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
.
• Master chip select CE0 blocks ADSP, but not ADSC
.
The AS7C33512PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are
available in a 100-pin 14×20 mm TQFP packaging.
.
Capacitance
Parameter
Symbol
Test conditions
= 0V
Max
Unit
pF
*
Input capacitance
C
V
5
7
IN
IN
*
I/O capacitance
C
V
= V = 0V
OUT
pF
I/O
IN
*
Guaranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
Typical
Units
°C/W
°C/W
1–layer
4–layer
θ
40
22
Thermal resistance
(junction to ambient)
JA
1
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
θ
JA
Thermal resistance
(junction to top of case)
θ
8
°C/W
1
JC
1 This parameter is sampled.
1. PowerPC™ is a trademark International Business Machines Corporation
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AS7C33512PFS18A
®
Signal descriptions
Signal
I/O Properties
Description
CLK
I
I
CLOCK Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.
A,A0,A1
SYNC
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
DQ[a,b] I/O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE0
I
I
SYNC
SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
Burst advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]
control write enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
BW[a,b]
OE
I
I
I
SYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
ASYNC
Selects Burst mode. When tied to V or left floating, device follows Interleaved Burst
DD
LBO
STATIC order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
ZZ
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
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AS7C33512PFS18A
®
Write enable truth table (per byte)
Function
GWE BWE
BWa
X
BWb
X
L
H
H
H
H
H
X
L
L
L
H
L
Write All Bytes
L
L
Write Byte a
Write Byte b
L
H
H
L
X
X
Read
H
H
Key: X = don’t care, L = low, H = high, n = a, b; BWE
,
BWn = internal write signal.
Asynchronous Truth Table
Operation
Snooze mode
ZZ
H
L
OE
X
I/O Status
High-Z
L
Dout
Read
L
H
High-Z
Write
L
X
Din, High-Z
High-Z
Deselected
L
X
Burst sequence table
Interleaved burst address (LBO = 1)
Linear burst address (LBO = 0)
A1 A0
0 0
A1 A0
0 1
A1 A0
1 0
A1 A0
1 1
A1 A0
0 0
A1 A0
0 1
A1 A0
1 0
A1 A0
1 1
Starting Address
First Increment
Second Increment
Third Increment
Starting Address
First Increment
Second Increment
Third Increment
0 1
0 0
1 1
1 0
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
1 1
1 0
0 1
1 0
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AS7C33512PFS18A
®
[4]
Synchronous truth table
[2]
CE01
H
L
CE1
X
L
CE2 ADSP ADSC ADV WRITE
OE
X
X
X
X
X
L
Address accessed
NA
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
X
X
X
H
H
L
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
NA
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
L
H
L
Next
Hi−Z
Q
H
H
L
Current
Current
Next
H
L
Hi−Z
Q
L
H
L
Next
Hi−Z
Q
H
H
X
L
Current
Current
External
Next
H
X
X
X
X
X
Hi−Z
3
D
X
H
X
H
X
X
X
X
H
H
H
H
L
D
D
D
D
L
L
Next
H
H
L
Current
Current
L
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE,
GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
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AS7C33512PFS18A
®
1
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–0.5
–
Max
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
V
, V
+4.6
DD
DDQ
V
V
+ 0.5
DD
V
IN
IN
V
V
+ 0.5
V
DDQ
P
1.8
W
D
DC output current
I
–
50
mA
°C
°C
OUT
Storage temperature (plastic)
Temperature under bias
T
–65
–65
+150
+135
stg
T
bias
1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
3.135
0
Nominal
Max
3.465
3.465
0
Unit
V
3.3
3.3
0
VDDQ
Vss
V
V
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
2.375
0
Nominal
Max
3.465
2.625
0
Unit
V
3.3
2.5
0
VDDQ
Vss
V
V
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AS7C33512PFS18A
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current1
Output leakage current
Sym
|ILI|
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
2
|ILO
|
-2
2*
2*
-0.3**
-0.5**
2.4
–
2
VDD+0.3
VDDQ+0.3
0.8
µA
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
V
V
Address and control pins
I/O pins
VIL
0.8
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
–
V
V
0.4
1 LBO and ZZ pins and the have an internal pull-up or pull-down, and input leakage = ±10 µA.
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current
Output leakage current
Sym
|ILI|
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
2
µA
µA
V
|ILO
|
-2
2
VDD+0.3
VDDQ+0.3
0.7
1.7*
1.7*
-0.3**
-0.3**
1.7
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
V
Address and control pins
I/O pins
V
VIL
0.7
V
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
–
V
–
0.7
V
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**
V
min = -1.5 for pulse width less than 0.2 X tCYC
IL
I
operating conditions and maximum limits
DD
Parameter
Sym
Conditions
-166
-133
Unit
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
,
Operating power supply
current1
ICC
475
425
mA
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or >
V
– 0.2V, Deselected,
DD
ISB
130
100
f = fMax, ZZ < VIL
Standby power supply
current
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
mA
ISB1
ISB2
30
30
30
30
Deselected, f = f , ZZ
≥
V
– 0.2V,
Max
DD
all VIN ≤ VIL or ≥ VIH
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
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AS7C33512PFS18A
®
Timing characteristics for 3.3 V I/O operation
–166
–133
1
Parameter
Clock frequency
Symbol
Min Max Min Max Unit
Notes
f
–
166
–
–
133
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Cycle time
t
6
7.5
-
CYC
Clock access time
t
-
3.5
3.5
–
4.0
4.0
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
OE
t
0
0
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
OH
t
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
–
4.0
4.0
–
t
–
–
HZC
t
0
0
OHOE
t
2.4
2.3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
5
5
CH
Clock low pulse width
t
t
t
–
–
CL
AS
DS
Address setup to clock high
Data setup to clock high
–
–
6
–
–
6
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 17
t
–
–
6,7
6,8
6
WS
t
–
–
CSS
t
–
–
AH
DH
WH
t
–
–
6
t
–
–
6,7
6,8
6
t
–
–
CSH
t
–
–
ADVS
t
–
–
6
ADSPS
ADSCS
t
–
–
6
t
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
6
t
–
–
6
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Alliance Semiconductor
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AS7C33512PFS18A
®
Timing characteristics for 2.5V I/O operation
–166
–133
1
Parameter
Clock frequency
Symbol Min Max Min Max Unit
Notes
f
–
166
–
–
133
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Cycle time
t
6
7.5
-
CYC
Clock access time
t
-
4.0
3.5
–
4.5
4.0
–
CD
Output enable LOW to data valid
Clock HIGH to output Low Z
Data output invalid from clock HIGH
Output enable LOW to output Low Z
Output enable HIGH to output High Z
Clock HIGH to output High Z
Output enable HIGH to invalid output
t
–
–
OE
t
0
0
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
OH
t
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
–
4.0
4.0
–
t
–
–
HZC
t
0
0
OHOE
Clock HIGH pulse width
t
2.4
2.3
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
0.7
0.7
0.7
–
2.5
2.5
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
0.7
0.7
0.7
–
5
5
.
CH
.
Clock LOW pulse width
t
t
t
–
–
CL
AS
DS
Address setup to clock HIGH
Data setup to clock HIGH
–
–
6
–
–
6
Write setup to clock HIGH
Chip select setup to clock HIGH
Address hold from clock HIGH
Data hold from clock HIGH
Write hold from clock HIGH
Chip select hold from clock HIGH
ADV setup to clock HIGH
ADSP setup to clock HIGH
ADSC setup to clock HIGH
ADV hold from clock HIGH
ADSP hold from clock HIGH
ADSC hold from clock HIGH
t
–
–
6,7
6,8
6
WS
t
–
–
CSS
t
–
–
AH
DH
WH
t
–
–
6
t
–
–
6,7
6,8
6
t
–
–
CSH
t
–
–
ADVS
t
–
–
6
ADSPS
ADSCS
t
–
–
6
t
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
6
t
–
–
6
1 See “Notes on page 17.
Snooze Mode Electrical Characteristics
Description
Conditions
ZZ > V
Symbol
Min
Max
Units
mA
Current during Snooze Mode
ZZ active to input ignored
I
30
IH
SB2
PDS
PUS
t
t
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
t
2
ZZI
t
0
RZZI
11/30/04; v.2.2
Alliance Semiconductor
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AS7C33512PFS18A
®
Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
LOAD NEW ADDRESS
A3
tAH
tAS
A1
A2
Address
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
ADV inserts wait states
t
OE
tCD
tHZC
tHZOE
tOH
tLZOE
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
Q(A1)
Dout
Read Suspend Read
Burst
Read
Burst
Read
Suspend
Read
2Ý10
Burst
Read
Read
Q(A3)
Burst
Read
3Ý01
Burst
Read
3Ý10
Burst
Read
3Ý11
) Q(A )
Q(A1)
Read
Q(A2)
DSEL
Q(A1)
2Ý01
2Ý10
2Ý11
Q(A
) Q(A
) Q(A
) Q(A
)
Q(A
) Q(A
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
11/30/04; v.2.2
Alliance Semiconductor
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AS7C33512PFS18A
®
Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
A3
tAS
tAH
A1
A2
Address
tWS
tWH
BWE
BW[a:b]
tCSS
tCSH
CE0, CE2
CE1
ADV SUSPENDS BURST
tADVH
tADVS
ADV
OE
tDS
tDH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Din
Read
Q(A1)
ADV
Burst
Write
Sus-
pend
Write
D(A1)
Suspend
Write
ADV
Burst
Write
Read
Q(A2)
ADV
Burst
Write
ADV
Burst
Write
Burst
Write
Suspend
Write
Write
3
D(A )
2
D(A )
3Ý01
2Ý01
D(A
)
D(A
)
2Ý01
D(A
)
3Ý10
2Ý10
2Ý11
D(A
)
D(A
)
D(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
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Alliance Semiconductor
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AS7C33512PFS18A
®
Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tAH
tAS
A2
A3
A1
Address
tWH
tWS
GWE
CE0, CE2
CE1
tADVH
tADVS
ADV
OE
tDH
tDS
Din
D(A2)
tOE
tCD
tLZC
tOH
tHZOE
tLZOE
Dout
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
DSEL
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Suspend
Write
Read
Q(A3)
ADV
Burst
Read
ADV
Burst
Read
ADV
Burst
Read
2
D(A )
3Ý01
3Ý10
3Ý11
Q(A )
Q(A
)
Q(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
11/30/04; v.2.2
Alliance Semiconductor
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AS7C33512PFS18A
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCYC
tCH
tCL
CLK
tADSCS
tADSCH
ADSC
tAS
tAH
A5
A7
A9
A1
A4
A6
A8
A3
A2
ADDRESS
tWS
tWH
GWE
CE0,CE2
CE1
tCSS
tCSH
ADV
OE
tOE
tLZOE
tOH
tHZOE
tLZOE
Q(A2)
Q(A1)
Q(A3)
Q(A8)
Q(A4)
Q(A9)
Dout
Din
tDH
tDS
D(A5)
D(A6)
D(A7)
READ
Q(A9)
WRITE
D(A7)
READ READ READ
Q(A1) Q(A2) Q(A3)
WRITE
D(A6)
READ
Q(A8)
READ
Q(A4)
WRITE
D(A5)
11/30/04; v.2.2
Alliance Semiconductor
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AS7C33512PFS18A
®
Timing waveform of power down cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPS
ADSP
ADSC
A2
A1
ADDRESS
GWE
tWS
tWH
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
tLZOE
Din
D(A2)
tHZOE
D(A2(Ý01))
tHZC
Dout
Q(A1)
tPUS
tPDS
ZZ Recovery Cycle
Normal Operation Mode
ZZ
ZZ Setup Cycle
tZZI
tRZZI
ISB2
Isupply
Sleep
State
READ
Q(A2)
CON-
TINUE
SUSPEND
WRITE
D(A2)
SUSPEND
READ
Q(A1)
READ
Q(A1)
WRITE
Ý01)
D(A2
11/30/04; v.2.2
Alliance Semiconductor
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AS7C33512PFS18A
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω / 1667Ω
Z0 = 50Ω
50
Ω
DOUT
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
+3.0V
DOUT
5 pF*
90%
10%
90%
10%
353Ω / 1538Ω
30 pF*
GND
*including scope
and jig capacitance
GND
for 2.5V I/O
Figure C: Output load (B)
Figure A: Input waveform
Figure B: Output load (A)
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured HIGH above VIH and tCL measured as LOW below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to GWE
,
BWE
,
BW[a,b]
.
8) Chip select refers to CE0
,
CE1
,
CE2.
11/30/04; v.2.2
Alliance Semiconductor
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AS7C33512PFS18A
®
Package Dimensions
100-pin quad flat pack (TQFP)
Hd
D
TQFP
Min
0.05
Max
0.15
A1
A2
b
b
e
1.35
1.45
α
0.22
0.38
0.09
0.20
c
13.90
19.90
14.10
20.10
D
He
E
E
0.65 nominal
e
15.90
21.90
0.45
16.10
22.10
0.75
Hd
He
L
c
L1
L
A1 A2
1.00 nominal
L1
0°
7°
α
Dimensions in millimeters
11/30/04; v.2.2
Alliance Semiconductor
18 of 20
AS7C33512PFS18A
®
Ordering information
Package
–166 MHz
–133 MHz
TQFP x18
AS7C33512PFS18A-166TQC
AS7C33512PFS18A-166TQI
AS7C33512PFS18A-133TQC
AS7C33512PFS18A-133TQI
TQFP x18
Note: Add suffix ‘N’ with the above part number for Lead Free Parts (Ex. AS7C33512PFS18A-166TQCN)
Part numbering guide
AS7C
33
512
PF
S
18
A
–XXX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
11
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization: 512=512K
4.Pipelined mode
5.Deselect: S=Single cycle deselect
6.Organization: 18=x18
7.Production version: A=first production version
8. Clock speed (MHz)
9. Package type: TQ=TQFP
10. Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
11. N = Lead free part
11/30/04; v.2.2
Alliance Semiconductor
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AS7C33512PFS18A
®
®
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33512PFS18A
Document Version: v.2.2
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alli-
ance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products
at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/
or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under develop-
ment, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential cus-
tomers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability
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相关型号：
AS7C33512PFS18A-100TQIN
Standard SRAM, 512KX18, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100
ALSC
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