AS7C3364PFS36A-150TQC [ALSC]
3.3V 64K X 32/36 pipeline burst synchronous SRAM; 3.3V 64K X 32/36管道爆裂的同步SRAM
| 型号： | AS7C3364PFS36A-150TQC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 64K X 32/36 pipeline burst synchronous SRAM |
| 文件： | 总11页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2001
Preliminary Information
AS7C3364PFS32A
AS7C3364PFS36A
®
3.3V 64K X 32/36 pipeline burst synchronous SRAM
Features
• Organization: 65,536 words × 32 or 36 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V
• 30 mW typical standby power in power down mode
DDQ
*
• Pentium® compatible architecture and timing
Pin arrangement
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CE
Burst logic
CLR
64K × 32/36
Memory
array
DQP /NC
b
DQP /NC
c
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
16
14
16
16
DQ
D
CE
CLK
Q
DQ
2
c
b
A[15:0]
Address
DQ
b
DQ
c
3
register
V
V
4
DDQ
DDQ
SSQ
c
V
V
5
SSQ
DQ
DQ
6
b
36/32
36/32
GWE
BWE
DQ
b
DQ
c
7
D
Q
Q
Q
Q
DQ
d
DQ
DQ
8
b
c
Byte write
BW
DQ
c
9
DQ
b
d
registers
V
V
10
11
12
13
14
15
SSQ
SSQ
CLK
V
V
DQ
DQ
c
DDQ
DDQ
DQ
b
D
c
DQ
c
DQ
b
BW
BW
c
Byte write
V
FT
DD
SS
registers
NC
VDD
ZZ
V
CLK
D
TQFP 14 × 20 mm
NC 16
V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ
SS
b
DQ
DQ
DQ
b
d
d
a
Byte write
DQ
a
registers
V
V
CLK
DDQ
DDQ
SSQ
d
d
d
d
V
V
SSQ
D
DQ
DQ
a
DQ
a
4
BW
DQ
a
DQ
DQ
DQ
V
a
Byte write
DQ
registers
a
CLK
D
DQ
a
V
SSQ
SSQ
CE0
CE1
CE2
V
V
OE
Output
registers
CLK
Q
Q
DDQ
DDQ
DQ
DQ
DQ
Input
registers
CLK
a
d
d
Enable
register
DQ
a
CE
CLK
DQP /NC
DQP /NC
a
d
D
Enable
Power
down
delay
ZZ
register
CLK
Note: Pins 1,30,51,80 are NC for ×32
OE
DATA [35:0]
DATA [31:0]
FT
Selection guide
AS7C3364PFS32A AS7C3364PFS32A AS7C3364PFS32A AS7C3364PFS32A
–166
–150
–133
7.5
133
4
–100
Units
ns
Minimum cycle time
6
6.7
10
Maximum clock frequency
166
3.5
475
130
30
150
3.8
100
5
MHz
ns
Maximum pipelined clock access time
Maximum operating current
450
110
30
425
100
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
*
®
Pentium is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this docu-
ment are the property of their respective owners.
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C3364PFS32A
AS7C3364PFS36A
®
Functional description
The AS7C3364PFS32A and AS7C3364PFS36A are high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 65,536 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given
technology.
Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC™*-based systems in computing, datacomm, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe
(ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High.
Burst operation is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium® count sequence. With
LBO driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to
the next burst address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip enable CE0 blocks ADSP, but not ADSC.
ASAS7C3364PFS32A and ASAS7C3364PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can
operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.
™
*PowerPC is a tradenark International Business Machines Corporation.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
Signals
Address and control pins
I/O pins
Test conditions
VIN = 0V
Max
5
Unit
pF
CI/O
VIN = VOUT = 0V
7
pF
Write enable truth table (per byte)
GWE
BWE
BWn
WEn
L
X
L
X
L
T
T
H
H
H
L
X
H
F*
F*
H
Key:
X = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE, WEn = internal write signal.
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AS7C3364PFS32A
AS7C3364PFS36A
®
Signal descriptions
I/
Signal
CLK
O
Properties
CLOCK
Description
I
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
A0–A15
I
SYNC
DQ[a,b,c,d] I/O SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE0
I
I
I
SYNC
SYNC
SYNC
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
ADSC
ADV
I
I
SYNC
SYNC
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
BW[a,b,c,d] I
SYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
OE
I
I
ASYNC
STATIC
default =
HIGH
Count mode. When driven High, count sequence follows Intel XOR convention. When
LBO
driven Low, count sequence follows linear convention. This signal is internally pulled High.18
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
FT
ZZ
I
I
STATIC
ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Symbol
DD, VDDQ
Min
–0.5
–0.5
–0.5
–
Max
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
V
+4.6
VIN
VIN
PD
VDD + 0.5
VDDQ + 0.5
1.8
V
V
W
mA
oC
oC
DC output current
IOUT
Tstg
Tbias
–
50
Storage temperature (plastic)
Temperature under bias
–65
–65
+150
+135
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
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AS7C3364PFS32A
AS7C3364PFS36A
®
Synchronous truth table
1
CE0
H
L
CE1
X
L
CE2 ADSP ADSC ADV WEn
OE Address accessed
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z2
Hi−Z
Hi−Z2
Hi−Z
Q
X
X
X
H
H
L
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
F
X
X
X
X
X
L
NA
NA
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
Begin read
Begin read
Begin read
Cont. read
Cont. read
Suspend read
Suspend read
Cont. read
Cont. read
Suspend read
Suspend read
Begin write
Cont. write
Cont. write
Suspend write
Suspend write
L
L
L
H
L
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
L
L
F
H
L
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
F
L
F
H
L
Next
Hi−Z
Q
H
H
L
F
Current
Current
Next
F
H
L
Hi−Z
Q
F
L
F
H
L
Next
Hi−Z
Q
H
H
X
L
F
Current
Current
External
Next
F
H
X
X
X
X
X
Hi−Z
D3
T
T
T
T
T
X
H
X
H
X
X
X
X
H
H
H
H
D
L
Next
D
H
H
Current
Current
D
D
Key: X = Don’t Care, L = Low, H = High.
1
See “Write enable truth table”on page 2 for more information.
Q in flow through mode.
For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time.
2
3
Recommended operating conditions
Parameter
Symbol
VDD
VSS
Min
3.135
0.0
Nominal
Max
3.6
Unit
3.3
0.0
3.3
0.0
2.5
0.0
–
Supply voltage
V
0.0
VDDQ
VSSQ
VDDQ
VSSQ
VIH
3.135
0.0
3.6
3.3V I/O supply
voltage
V
V
V
0.0
2.35
0.0
2.9
2.5V I/O supply
voltage
0.0
2.0
–0.5*
VDD + 0.3
0.8
Address and
control pins
VIL
–
Input voltages†
VIH
2.0
–
VDDQ + 0.3
0.8
I/O pins
V
VIL
–0.5*
0
–
Ambient operating temperature
TA
–
70
°C
* V min = –2.0V for pulse width less than 0.2 × t
.
IL
RC
† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
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AS7C3364PFS32A
AS7C3364PFS36A
®
TQFP thermal resistance
Description
Conditions
Symbol
Typical
Units
Thermal resistance
θJA
46
°C/W
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per EIA/
JESD51
(junction to ambient)*
Thermal resistance
θJC
2.8
°C/W
(junction to top of case)*
* This parameter is sampled.
DC electrical characteristics
–166
–150
–133
–100
Parameter
Symbol
Test conditions
VDD = Max, VIN = GND to VDD
OE ≥ VIH, VDD = Max,
Min Max Min Max Min Max Min Max Unit
Input leakage
current*
|ILI|
–
–
2
2
–
–
2
2
–
–
2
2
–
–
2
2
µA
µA
Output leakage
current
|ILO
|
VOUT = GND to VDD
Operating power
supply current
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA
ICC
ISB
ISB1
ISB2
–
–
–
475
130
30
–
–
–
450
110
30
–
–
–
425
100
30
–
–
–
325 mA
90
Deselected, f = fMax, ZZ ≤ VIL
Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Standby power
supply current
30
mA
Deselected, f = f , ZZ
≥
V
– 0.2V
Max
DD
–
30
–
30
–
30
–
30
All VIN ≤ VIL or ≥ VIH
VOL
IOL = 8 mA, VDDQ = 3.465V
IOH = –4 mA, VDDQ = 3.135V
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
V
Output voltage
VOH
2.4
2.4
2.4
2.4
–
* LBO pin has an internal pull-up and input leakage = 10 µa.
Note: ICC given with no output loading. ICC increases with faster cycles times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
–166
–150
–133
–100
Parameter
Symbol
|ILO
Test conditions
Min Max Min Max Min Max Min Max Unit
Output leakage
current
OE ≥ VIH, VDD = Max,
OUT = GND to VDD
|
–1
1
–1
1
–1
1
–1
1
µA
V
V
VOL
IOL = 2 mA, VDDQ = 2.65V
IOH = –2 mA, VDDQ = 2.35V
–
0.7
–
–
0.7
–
–
0.7
–
–
0.7
–
Output voltage
VOH
1.7
1.7
1.7
1.7
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AS7C3364PFS32A
AS7C3364PFS36A
®
Timing characteristics over operating range
–166
–150
–133
–100
Symbo
Notes
*
Parameter
Clock frequency
l
Min Max Min Max Min Max Min Max Unit
fMax
tCYC
tCYCF
tCD
–
6
166
–
–
6.7
10
–
150
–
–
7.5
12
–
133
–
–
10
12
–
100 MHz
Cycle time (pipelined mode)
–
–
ns
ns
ns
Cycle time (flow-through mode)
Clock access time (pipelined mode)
10
–
–
–
–
3.5
3.8
4.0
5.0
Clock access time (flow-through
mode)
tCDF
–
9
–
10
–
10
–
12
ns
Output enable LOW to data valid
Clock HIGH to output Low Z
tOE
tLZC
tOH
–
3.5
–
–
3.8
–
–
4.0
–
–
5.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
2,3,4
2
Data output invalid from clock HIGH
Output enable LOW to output Low Z
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
–
tLZOE
–
–
–
–
2,3,4
2,3,4
2,3,4
Output enable HIGH to output High Z tHZOE
Clock HIGH to output High Z tHZC
Output enable HIGH to invalid output tOHOE
–
3.5
3.5
–
–
3.8
3.8
–
–
4.0
4.0
–
–
4.5
5.0
–
–
–
–
–
0
0
0
0
Clock HIGH pulse width
tCH
tCL
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
3.5
3.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
5
5
Clock LOW pulse width
–
–
–
–
Address setup to clock HIGH
Data setup to clock HIGH
Write setup to clock HIGH
Chip select setup to clock HIGH
Address hold from clock HIGH
Data hold from clock HIGH
Write hold from clock HIGH
Chip select hold from clock HIGH
ADV setup to clock HIGH
ADSP setup to clock HIGH
ADSC setup to clock HIGH
ADV hold from clock HIGH
ADSP hold fromclock HIGH
ADSC hold from clock HIGH
tAS
–
–
–
–
6
tDS
–
–
–
–
6
tWS
tCSS
tAH
tDH
tWH
tCSH
tADVS
–
–
–
–
6,7
6,8
6
–
–
–
–
–
–
–
–
–
–
–
–
6
–
–
–
–
6,7
6,8
6
–
–
–
–
–
–
–
–
tADSPS 1.5
tADSCS 1.5
–
–
–
–
6
–
–
–
–
6
tADVH
0.5
–
–
–
–
6
tADSPH 0.5
tADSCH 0.5
–
–
–
–
6
–
–
–
–
6
*See “Notes” on page 10.
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
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AS7C3364PFS32A
AS7C3364PFS36A
®
Timing waveform of read cycle
t
t
CYC
CL
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
ADSC
t
ADSCS
t
ADSCH
t
AS
LOAD NEW ADDRESS
A3
t
AH
A1
A2
Address
t
WS
t
WH
GWE, BWE
t
CSS
t
CSH
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
CD
t
HZOE
t
OH
ADV INSERTS WAIT STATES
t
HZC
Q(A1)
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
D
OUT
(pipelined mode)
t
OE
t
LZOE
Q(A1)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)
D
OUT
(flow-through mode)
t
HZC
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
BW[a:d] is don’t care.
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Alliance Semiconductor
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AS7C3364PFS32A
AS7C3364PFS36A
®
Timing waveform of write cycle
t
t
CYC
CL
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
t
ADSCS
t
ADSCH
ADSC
ADSC LOADS NEW ADDRESS
A3
t
AS
t
AH
A1
A2
Address
t
WS
t
WH
BWE
BW[a:d]
t
CSS
t
CSH
CE0, CE2
CE1
t
ADV SUSPENDS BURST
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01)
D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Data In
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
2/1/01
Alliance Semiconductor
P. 8 of 11
AS7C3364PFS32A
AS7C3364PFS36A
®
Timing waveform of read/write cycle
t
t
CYC
CL
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
t
AS
t
AH
A2
A3
A1
Address
t
WS
t
WH
GWE
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A2)
D
IN
t
t
t
t
LZOE
HZOE
OH
LZC
t
t
OE
CD
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
D
OUT
(pipeline mode)
t
CDF
Q(A3Ý11)
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
D
OUT
(flow-through mode)
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
2/1/01
Alliance Semiconductor
P. 9 of 11
AS7C3364PFS32A
AS7C3364PFS36A
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
Thevenin equivalent:
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O
317
Ω
Z = 50
Ω
50
Ω
0
D
V = 1.5V
OUT
+3.0V
D
OUT
L
90%
10%
90%
10%
5 pF*
for 3.3V I/O;
30 pF*
351
Ω
= V
/2
DDQ
GND *including scope
and jig capacitance
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes
1
2
3
4
5
6
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
is less than t
; and t
is less than t
at any given temperature and voltage.
LZC
HZOE
LZOE
HZC
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
Chip select refers to CE0
,
BWE
,
BW[a:d].
CE2
,
CE1
,
.
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Hd
D
Min
0.05
1.35
0.22
0.09
13.90
19.90
Max
0.15
1.45
0.38
0.20
14.10
20.10
A1
A2
b
b
e
c
D
E
e
0.65 nominal
Hd
He
L
15.90
21.90
0.45
16.10
22.10
0.75
He
E
L1
α
1.00 nominal
0°
7°
Dimensions in millimeters
c
L1
L
α
A1 A2
2/1/01
Alliance Semiconductor
P. 10 of 11
AS7C3364PFS32A
AS7C3364PFS36A
®
Ordering information
–166 MHz
–150 MHz
–133 MHz
–100 MHz
AS7C3364PFS32A-166TQC
AS7C3364PFS32A-166TQI
AS7C3364PFS36A-166TQC
AS7C3364PFS36A-166TQI
AS7C3364PFS32A-150TQC
AS7C3364PFS32A-150TQI
AS7C3364PFS36A-150TQC
AS7C3364PFS36A-150TQI
AS7C3364PFS32A-133TQC
AS7C3364PFS32A-133TQI
AS7C3364PFS36A-133TQC
AS7C3364PFS36A-133TQI
AS7C3364PFS32A-100TQC
AS7C3364PFS32A-100TQI
AS7C3364PFS36A-100TQC
AS7C3364PFS36A-100TQI
Part numbering guide
AS7C
33
64
PF
S
32/36
A
–XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
10
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization: 64=64K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: S=Single cycle deselect
6.Organization: 32=x32; 36=x36
7.Production version: A=first production version
8.Clock speed (MHz)
9.Package type: TQ=TQFP
10.Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
2/1/01; V.0.9
Alliance Semiconductor
P. 11 of 11
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