AS7C34096-10TCH [ALSC]
Standard SRAM, 512KX8, 10ns, CMOS, PDSO44, TSOP2-44;
| 型号： | AS7C34096-10TCH |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 512KX8, 10ns, CMOS, PDSO44, TSOP2-44 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2001
AS7C4096
AS7C34096
®
5V/3.3V 512K × 8 CMOS SRAM
Features
• AS7C4096 (5V version)
• Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4096) / max @ 12 ns
- 468 mW (AS7C34096) / max @ 12 ns
Pin arrangements
Logic block diagram
36-pin SOJ (400 mil)
44-pin TSOP 2
NC
NC
NC
NC
NC
A18
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
2
V
CC
2
A18
A17
A16
A15
OE
A0
A1
3
A2
3
4
GND
A3
4
A2
A17
A16
A15
OE
5
A4
5
A3
6
Input buffer
CE
6
A4
7
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A5
7
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
CE
8
8
I/O1
I/O2
VCC
I/O8
I/O7
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
GND
I/O1
I/O8
VCC
GND
I/O3
I/O4
WE
A5
524,288 × 8
Array
(4,194,304)
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A6
A7
A6
A8
A7
A9
A8
A9
A9
NC
NC
NC
NC
Column decoder
WE
OE
CE
Control
Circuit
48-CSP/BGA Package
1
2
3
4
5
6
A
B
A0
A1
NC
WE
NC
NC
NC
A18
CS
A3
A6
A8
I/O5
I/O6
VSS
A2
A4
A7
I/O1
I/O2
VCC
C
D
E
NC
NC
NC
NC
OE
A10
A5
NC
NC
NC
NC
NC
NC
A17
A16
A12
VCC
I/O7
I/O8
A9
VSS
F
I/O3
I/O4
A14
G
H
A15
A13
A11
Selection guide
–10
10
5
–12
–15
–20
20
Unit
Maximum address access time
12
6
15
7
ns
Maximum outputenable access time
9
ns
AS7C4096
AS7C34096
AS7C4096
AS7C34096
–
250
130
20
220
110
20
180
100
20
mA
mA
mA
mA
Maximum operating current
160
–
Maximum CMOS standby current
20
20
20
20
11/28/01; v.1.7
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
AS7C4096
AS7C34096
®
Functional description
The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The AS7C4096 is guaranteed not to exceed 110 mW power consumption in
CMOS standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single supply voltage. Both devices are available in the
industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
Absolute maximum ratings
Parameter
Device
Symbol
Vt1
Min
–1
Max
+7.0
+5.0
VCC +0.5
1.0
Unit
V
AS7C4096
AS7C34096
Voltage on VCC relative to GND
Vt1
–0.5
–0.5
–
V
Voltage on any pin relative to GND
Power dissipation
Vt2
V
PD
W
°C
°C
mA
Storage temperature (plastic)
Temperature with VCC applied
DC current unto output (low)
Tstg
–65
–55
–
+150
+125
20
Tbias
IOUT
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
WE
X
OE
X
Data
High Z
High Z
DOUT
DIN
Mode
Standby (ISB, ISB1
)
H
H
L
Output disable (ICC)
Read (ICC)
L
H
L
L
X
Write (ICC)
Key: X = Don’t care, L = Low, H = High
11/28/01; v.1.7
Alliance Semiconductor
P. 2 of 10
AS7C4096
AS7C34096
®
Recommended operating condition
Parameter
Device
Symbol
Min
4.5
Nominal
Max
5.5
Unit
V
AS7C4096
AS7C34096
AS7C34096
AS7C4096
AS7C34096
VCC(12/15/20)
5.0
3.30
3.3
–
Supply voltage
Input voltage
VCC (–10)
3.15
3.0
3.6
V
VCC(10*/12/15/20)
3.6
V
VIH
VIH
VIL
TA
2.2
VCC + 0.5
VCC + 0.5
0.8
V
2.0
–0.5††
–
V
–
V
commercial
industrial
0
–
70
°C
°C
Ambient operating
temperature
TA
–40
–
85
ꢀꢁꢂꢃꢄꢅꢁꢆꢇꢈꢅꢉꢊꢄꢋꢁꢌꢇꢄꢊꢍꢇꢌꢁꢎꢏꢁꢅꢐꢑꢑꢉꢒꢁOꢓPꢋꢁꢔꢆꢔꢉꢕꢔꢎꢕꢇꢁꢉꢄꢁꢖꢊꢗꢗꢇꢈꢉꢖꢔꢕꢁꢍꢇꢗꢘꢇꢈꢔꢍꢐꢈꢇꢁꢈꢔꢄꢙꢇꢁꢊꢄꢕꢏ
ꢚꢁV min = –3.0V for pulse width less than t /2.
IL RC
ꢀ
DC operating characteristics (over the operating range)
–10
–12
–15
–20
Parameter Symbol
Test conditions
Device
Min Max Min Max Min Max Min Max Unit
Input leakage
|ILI|
VCC = Max, VIN = GND to VCC
–
1
–
1
–
1
–
1
µA
current
Output
leakage
current
VCC = Max, CE = VIH
VOUT= GND to VCC
|ILO|
–
1
–
1
–
1
–
1
µA
Operating
power supply ICC
current
AS7C4096
–
–
–
–
–
250
130
–
–
220
110
–
–
180 mA
100
VCC = Max, CE < VIL
f = fMax, IOUT = 0mA
AS7C34096
160
AS7C4096
AS7C34096
AS7C4096
–
–
–
–
60
–
–
–
–
60
60
20
–
–
–
60
60
20
–
–
–
60
VCC = Max, CE = VIH
f = fMax, IOUT = 0mA
ISB
mA
60
Standby
power supply
VCC = Max,
20
current
ISB1 CE ≥ VCC – 0.2V, VIN ≤ 0.2V or VIN
CC – 0.2V, f = 0
≥
mA
AS7C34096
–
20
–
20
–
20
–
20
V
VOL
IOL = 8 mA, VCC = Min
IOH = –4 mA, VCC = Min
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
Output
voltage
VOH
2.4
2.4
2.4
2.4
ꢁ
Capacitance (f = 1MHz, T = 25° C, V = NOMINAL)
a
CC
Symbol
Parameter
Signals
Test conditions
VIN = 0V
Max
Unit
pF
Input capacitance
I/O capacitance
CIN
A, CE, WE, OE
I/O
5
7
CI/O
VIN = VOUT = 0V
pF
11/28/01; v.1.7
Alliance Semiconductor
P. 3 of 10
AS7C4096
AS7C34096
®
ꢂꢃꢆ
Read cycle (over the operating range)
–10
–12
–15
–20
Parameter
Read cycle time
Symbol Min
Max
–
Min
12
–
Max
–
Min
15
–
Max
–
Min
20
–
Max Unit Notes
tRC
tAA
tACE
tOE
10
–
–
20
20
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
10
10
5
12
12
6
15
15
7
3
3
Chip enable (CE) access time
Output enable (OE) access time
–
–
–
–
–
–
–
–
Output hold from address change tOH
3
3
–
–
3
–
3
–
3
–
5
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
tCLZ
tCHZ
tOLZ
tOHZ
tPU
–
3
–
0
–
0
–
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
5
–
6
–
7
–
9
0
–
–
0
–
0
–
0
–
5
–
6
–
7
–
9
0
–
–
0
–
0
–
0
–
Power down time
tPD
10
–
12
–
15
–
20
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
ꢂꢃꢄꢃꢅꢃꢆ
Read waveform 1 (address controlled)
t
RC
Address
t
AA
t
OH
D
Data valid
OUT
ꢂꢃꢄꢃꢇꢃꢆ
Read waveform 2 (CE, OE controlled)
t
RC1
CE
t
OE
OE
t
t
OHZ
OLZ
t
t
ACE
CHZ
D
OUT
Data valid
t
CLZ
t
PD
I
I
CC
t
Supply
current
PU
SB
50%
50%
11/28/01; v.1.7
Alliance Semiconductor
P. 4 of 10
AS7C4096
AS7C34096
®
ꢀꢀ
Write cycle (over the operating range)
–10
–12
–15
–20
Parameter
Write cycle time
Symbol Min
Max
–
Min
12
8
Max
–
Min
15
10
10
0
Max
–
Min
20
12
12
0
Max Unit Notes
tWC
tCW
tAW
tAS
10
7
–
–
–
–
–
–
–
–
–
–
9
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable (CE) to write end
Address setup to write end
Address setup time
–
–
–
7
–
8
–
–
0
–
0
–
–
Write pulse width (OE = high)
Write pulse width (OE = low
Address hold from end of write
Write recovery time
tWP1
tWP2
tAH
7
–
8
–
10
15
0
–
12
20
0
10
0
–
12
0
–
–
–
–
–
tWR
tDW
tDH
tWZ
tOW
0
–
0
–
0
–
0
Data valid to write end
5
–
6
–
7
–
9
Data hold time
0
–
0
–
0
–
0
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
0
5
0
6
0
7
0
3
–
3
–
3
–
3
ꢀꢈꢃꢀꢀ
Write waveform 1 (WE controlled)
t
WC
t
WR
t
t
AW
AH
Address
WE
t
WP
t
AS
t
t
DW
DH
D
Data valid
IN
t
t
WZ
OW
D
OUT
ꢀꢈꢃꢀꢀ
Write waveform 2 (CE controlled)
t
WC
t
WR
t
t
AH
AW
Address
t
t
CW
AS
CE
t
WP
WE
t
t
t
WZ
DW
DH
D
Data valid
IN
D
OUT
11/28/01; v.1.7
Alliance Semiconductor
P. 5 of 10
AS7C4096
AS7C34096
®
AC test conditions
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figures A, B, and C.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168W
D
D
+1.728V
OUT
+5V
+3.3V
320W
480W
+3.0V
GND
D
OUT
OUT
90%
10%
90%
10%
255W
C(14)
GND
350W
C(14)
GND
2 ns
Figure A: Input pulse
Figure C: 3.3V Output load
Figure B: 5V Output load
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
and t
are specified with C = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
11/28/01; v.1.7
Alliance Semiconductor
P. 6 of 10
AS7C4096
AS7C34096
®
ꢀꢁꢉ
Typical DC and AC characteristics
Normalized supply current I , I
Normalized supply current I , I
Normalized supply current I
SB1
CC SB
CC SB
vs. supply voltage V
vs. ambient temperature T
vs. ambient temperature T
CC
a
a
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
625
25
I
I
I
V
= V (NOMINAL)
CC
CC
CC
CC
5
1
I
SB
SB
0.2
0.04
MIN
NOMINAL
–55
–10
Ambient temperature (
Normalized access time t
35
80
125
–55
–10
35
80
MAX
125
Supply voltage (V)
°
C)
Ambient temperature (
°
C)
Normalized access time t
vs. supply voltage V
Normalized supply current I
CC
vs. cycle frequency 1/t , 1/t
RC WC
AA
AA
a
vs. ambient temperature T
CC
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
= V (NOMINAL)
V
= V (NOMINAL)
CC
CC
CC CC
T = 25° C
a
T = 25
°
C
a
MIN
NOMINAL
–55
–10
Ambient temperature (
Output sink current I
35
80
0
25
50
75
MAX
125
100
Supply voltage (V)
°
C)
Cycle frequency (MHz)
Typical access time change ∆t
AA
vs. output capacitive loading
V = V (NOMINAL)
CC
Output source current I
vs. output voltage V
OH
OH
OL
vs. output voltage V
OL
140
120
100
80
140
120
100
80
35
30
25
20
15
10
5
V
= V (NOMINAL)
V
= V (NOMINAL)
CC
CC
CC
CC
CC
T = 25
°
C
T = 25° C
a
a
60
60
40
40
20
20
0
0
0
0
0
0
250
500
750
1000
V
V
CC
CC
Output voltage (V)
Output voltage (V)
Capacitance (pF)
11/28/01; v.1.7
Alliance Semiconductor
P. 7 of 10
AS7C4096
AS7C34096
®
Package dimensions
c
44434241403938373635343332313029282726
252423
44-pin TSOP 2
Min(mm) Max(mm)
A
A1
A2
b
1.2
E
E1
44-pin TSOP 2
0.05
0.95
0.30
0.15
1.05
0.45
1 2 3 4 5 6 7 8 9 10111213141516171819202122
c
0.15 (typical)
d
d
18.28
10.03
11.56
18.54
10.16
11.96
E1
E
L
A
2
A
0–5°
e
0.80 (typical)
A
1
e
b
L
0.40
0.60
36-pin SOJ 400
Min(mils) Max(mils)
A
.128
0.148
–
D
A1
0.027
e
b
A2
b
0.102 NOM
E E
0.015
0.026
0.007
.920
0.020
0.032
0.013
.930
A
1
2
ꢛꢜ ꢘꢉꢄꢁ!"#
A1
b1
c
Seating
Plane
b
1
Pin 1
D
e
c
A2
0.045
0.055
E
0.400 NOM
E
E
0.435
0.445
11/28/01; v.1.7
Alliance Semiconductor
P. 8 of 10
AS7C4096
AS7C34096
®
48-ball FBGA
Detail View
A
Side View
E2
D
E
E2
Y
E
Die
Die
E1
5
0.3/Typ
Bottom View
Top View
Ball #A1 index
6
4
3
2
1
Ball #A1
A
B
C
D
E
SRAM Die
C
C1
F
A
G
H
Elastomer
A
B
B1
Notes
48-ball FBGA
Minimum Typ i c a l Maximum
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
A
–
6.90
–
0.75
7.00
3.75
11.00
5.25
0.35
–
–
7.10
–
B
B1
C
4. All tolerance are 0.050 unless otherwise specified.
5. Typ: typical.
10.90
–
11.10
–
C1
D
6. Y is coplanarity: 0.08 (max).
0.30
–
0.40
1.20
–
E
E1
E2
Y
–
0.68
0.25
–
0.22
–
0.27
0.08
11/28/01; v.1.7
Alliance Semiconductor
P. 9 of 10
AS7C4096
AS7C34096
®
Ordering codes
Package
Ver sion
10 ns
12 ns
15 ns
20 ns
5V commercial
5V industrial
NA
AS7C4096-12JC
AS7C4096-12JI
AS7C34096-12JC
AS7C34096-12JI
AS7C4096-12TC
AS7C4096-12TI
AS7C34096-12TC
AS7C34096-12TI
AS7C4096-12BC
AS7C4096-12BI
AS7C34096-12BC
AS7C34096-12BI
AS7C4096-15JC
AS7C4096-15JI
AS7C34096-15JC
AS7C34096-15JI
AS7C4096-15TC
AS7C4096-15TI
AS7C34096-15TC
AS7C34096-15TI
AS7C4096-15BC
AS7C4096-15BI
AS7C34096-15BC
AS7C34096-15BI
AS7C4096-20JC
AS7C4096-20JI
AS7C34096-20JC
AS7C34096-20JI
AS7C4096-20TC
AS7C4096-20TI
AS7C34096-20TC
AS7C34096-20TI
AS7C4096-20BC
AS7C4096-20BI
AS7C34096-20BC
AS7C34096-20BI
NA
SOJ
3.3V commercial
3.3V industrial
5V commercial
5V industrial
AS7C34096-10JC
NA
NA
NA
TSOP 2
BGA
3.3V commercial
3.3V industrial
5V commercial
5V industrial
AS7C34096-10TC
NA
NA
NA
AS7C34096-10BC
NA
3.3V commercial
3.3V industrial
Part numbering system
AS7C
X
4096
–XX
J, T, or B
X
Blank or H
Packages:
J: SOJ 400 mil
T: TSOP 2
Voltage:
Blank: 5V CMOS
3: 3.3V CMOS
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
SRAM
prefix
Device
number
Access
time
“H” denotes 10 ns
@ 3.0 - 3.6 V VCC
B: 48-ball FBGA 7x11 mm
11/28/01; v.1.7
Alliance Semiconductor
P. 10 of 10
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trade-
marks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under
development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or
implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as
express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting sys-
tems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
相关型号：
©2020 ICPDF网 联系我们和版权申明