AS7C512-35SC [ALSC]

Standard SRAM, 64KX8, 35ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOIC-32;
AS7C512-35SC
型号: AS7C512-35SC
厂家: ALLIANCE SEMICONDUCTOR CORPORATION    ALLIANCE SEMICONDUCTOR CORPORATION
描述:

Standard SRAM, 64KX8, 35ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOIC-32

静态存储器 光电二极管 内存集成电路
文件: 总8页 (文件大小:286K)
中文:  中文翻译
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High Performance  
64K×8  
AS7C512  
AS7C512L  
CMOS SRAM  
®
64K×8 CMOS SRAM  
Features  
• Easy memory expansion with CE1, CE2, OE inputs  
• Organization: 65,536 words × 8 bits  
• TTL-compatible, three-state I/O  
- 32-pin JEDEC standard packages  
- 300 mil PDIP and SOJ  
Socket compatible with 7C256 and 7C1024  
- 525 mil SOIC  
• High speed  
- 12/15/20/25/35 ns address access time  
- 3/4/5/6/8 ns output enable access time  
• Low power consumption  
- Active: 688 mW max (12 ns cycle)  
- Standby:27.5 mW max, CMOS I/O  
4.25 mW max, CMOS I/O, L version  
- Very low DC component in active power  
• 2.0V data retention (L version)  
• Equal access and cycle times  
• ESD protection > 2000 volts  
• Latch-up current > 200 mA  
Logic block diagram  
Pin arrangement  
TSOP 8×20  
DIP, SOJ, SOIC  
Vcc  
GND  
NC  
NC  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
I/O0  
I/O1  
I/O2  
GND  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Vcc  
A15  
CE2  
WE  
A13  
A8  
A9  
A11  
OE  
A10  
CE1  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
Input buffer  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
I/O7  
I/O0  
256×256×8  
Array  
(524,288)  
9
10  
11  
12  
13  
14  
15  
16  
WE  
OE  
Column decoder  
Control  
circuit  
CE1  
CE2  
A
8
A A A A A A A  
9 10 11 12 13 14 15  
Selection guide  
7C512-12 7C512-15 7C512-20 7C512-25 7C512-35  
Unit  
ns  
Maximum address access time  
Maximum output enable access time  
Maximum operating current  
12  
3
15  
4
20  
5
25  
6
35  
8
ns  
125  
5.0  
0.75  
115  
5.0  
0.75  
105  
5.0  
0.75  
95  
80  
mA  
mA  
mA  
5.0  
0.75  
5.0  
0.75  
Maximum CMOS standby current  
L
ALLIANCE SEMICONDUCTOR  
AS7C512  
Functional description  
The AS7C512 is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) organized as 65,536 words × 8 bits. It is  
designed for memory applications where fast data access, low power, and simple interfacing are desired.  
Equal address access and cycle times (t , t , t ) of 12/15/20/25/35 ns with output enable access times (t ) of 3/4/5/6/8 ns are ideal  
AA RC WC  
OE  
for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank  
memory systems.  
When CE1 is HIGH or CE2 is LOW the device enters standby mode. The standard AS7C512 is guaranteed not to exceed 27.5 mW power  
consumption in standby mode; the L version is guaranteed not to exceed 4.25 mW, and typically requires only 800 µW. The L version also  
offers 2.0V data retention, with maximum power of 400 µW.  
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written  
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external  
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).  
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip  
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is  
active, output drivers stay in high-impedance mode.  
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C512 is packaged in all high volume  
industry standard packages.  
Absolute maximum ratings  
Parameter  
Symbol  
Min  
–0.5  
Max  
Unit  
V
Voltage on any pin relative to GND  
Power dissipation  
V
+7.0  
1.0  
t
P
W
D
o
Storage temperature (plastic)  
Temperature under bias  
DC output current  
T
T
–55  
–10  
+150  
+85  
20  
C
stg  
bias  
out  
o
C
I
mA  
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-  
imum rating conditions for extended periods may affect reliability.  
Truth table  
CE1  
H
X
CE2  
X
WE  
X
OE  
X
Data  
Mode  
Standby (I , I  
High-Z  
High-Z  
High-Z  
)
)
SB SB1  
L
X
X
Standby (I , I  
SB SB1  
L
H
H
H
H
H
L
H
L
Output Disable  
Read  
L
D
D
out  
in  
L
X
Write  
Key: X = Don’t Care, L = LOW, H = HIGH  
Recommended operating conditions  
(T = 0°C to +70°C)  
a
Parameter  
Symbol  
Min  
4.5  
0.0  
2.2  
–0.5  
Typ  
5.0  
0.0  
Max  
5.5  
0.0  
Unit  
V
V
CC  
Supply voltage  
GND  
V
V
V
V
+1  
CC  
V
IH  
IL  
Input voltage  
0.8  
V
VIL min = –3.0V for pulse width less than tRC/2  
2
AS7C512  
DC operating characteristics1  
(V = 5V±10%, GND = 0V, T = 0°C to +70°C)  
CC  
a
-12  
-15  
-20  
-25  
-35  
Parameter  
Symbol Test Conditions  
Min Max Min Max Min Max Min Max Min Max Unit  
Input leakage  
current  
V
V
= Max,  
= GND to V  
CC  
in  
|I |  
1
1
1
1
1
1
1
1
1
1
µA  
µA  
LI  
CC  
CE1 = V or CE2 = V ,  
V
V
IH  
= Max,  
= GND to V  
IL  
Output leakage  
current  
|I  
|
LO  
CC  
out  
CC  
Operating  
power supply  
current  
125  
120  
115  
110  
105  
100  
95  
90  
80 mA  
75 mA  
CE1 = V , CE2 = V ,  
IL  
IH  
I
I
I
CC  
SB  
f = f  
I
= 0 mA  
L
L
L
max, out  
45  
40  
35  
30  
35  
30  
30  
25  
25 mA  
20 mA  
5.0 mA  
CE1 = V or CE2 = V ,  
IH  
IL  
f = f  
Standby  
power supply  
current  
max  
CE1 V –0.2V or CE2 0.2V,  
5.0  
5.0  
5.0  
5.0  
CC  
V
0.2V or V V –0.2V,  
SB1  
in  
in CC  
0.75  
0.75  
0.75  
0.75  
0.75 mA  
f = 0  
V
V
I
I
= 8 mA, V = Min  
0.4  
0.4  
0.4  
0.4  
0.4  
V
V
OL  
OL  
CC  
Output voltage  
= –4 mA, V = Min  
2.4  
2.4  
2.4  
2.4  
2.4  
OH  
OH  
CC  
Capacitance2  
(f = 1 MHz, T = Room Temperature, V = 5V)  
a
CC  
Parameter  
Symbol  
Signals  
Test Conditions  
Max  
5
Unit  
pF  
C
A, CE1, CE2, WE, OE  
I/O  
V
V
= 0V  
Input capacitance  
I/O capacitance  
IN  
in  
in  
C
= V = 0V  
7
pF  
I/O  
out  
Read cycle  
(V = 5V±10%, GND = 0V, T = 0°C to +70°C)  
CC a  
-12  
-15  
-20  
-25  
-35  
Parameter  
Symbol  
Unit Notes  
ns  
Min Max Min Max Min Max Min Max Min Max  
Read cycle time  
t
t
t
t
t
t
t
t
t
12  
3
3
3
0
0
12  
12  
12  
3
15  
3
3
3
0
0
15  
15  
15  
4
20  
3
3
3
0
0
20  
20  
20  
5
25  
3
3
3
0
0
25  
25  
25  
6
35  
3
3
3
0
0
35  
35  
35  
8
RC  
Address access time  
ns  
ns  
ns  
ns  
ns  
3
AA  
3, 12  
3, 12  
Chip enable (CE1) access time  
ACE1  
Chip enable (CE2) access time  
ACE2  
OE  
Output enable (OE) access time  
Output hold from address change  
Chip enable (CE1) to output in Low Z  
Chip enable (CE2) to output in Low Z  
Chip disable (CE1) to output in High Z  
5
OH  
ns 4, 5, 12  
ns 4, 5, 12  
ns 4, 5, 12  
ns 4, 5, 12  
CLZ1  
CLZ2  
CHZ1  
CHZ2  
OLZ  
OHZ  
PU  
3
4
5
6
8
Chip disable (CE2) to output in High Z t  
3
4
5
6
8
Output enable to output in Low Z  
Output disable to output in High Z  
Chip enable to power up time  
t
t
t
t
ns  
ns  
4, 5  
4, 5  
3
4
5
6
8
ns 4, 5, 12  
ns 4, 5, 12  
Chip disable to power down time  
12  
15  
20  
25  
35  
PD  
3
AS7C512  
Key to switching waveforms  
Rising input  
Falling input  
Undefined output/don’t care  
Read waveform 13,6,7,9,12  
Address controlled  
t
RC  
Address  
t
AA  
t
OH  
D
Data Valid  
out  
Read waveform 23,6,8,9,12  
CE1 and CE2 controlled  
1
t
RC  
CE1  
CE2  
OE  
t
OE  
t
t
OHZ  
OLZ  
t
t
CHZ1, CHZ2  
t
t
ACE1, ACE2  
D
out  
Data Valid  
t
CLZ1, tCLZ2  
t
PD  
I
I
CC  
SB  
t
PU  
Supply  
current  
50%  
50%  
Write cycle11,12  
(V = 5V±10%, GND = 0V, T = 0°C to +70°C)  
CC a  
-12  
-15  
-20  
-25  
-35  
Parameter  
Symbol  
Min Max Min Max Min Max Min Max Min Max Unit Notes  
Write cycle time  
t
t
t
t
t
t
t
t
t
t
t
12  
10  
10  
10  
0
5
15  
10  
10  
10  
0
5
20  
12  
12  
12  
0
5
20  
15  
15  
15  
0
5
30  
20  
20  
20  
0
5
ns  
WC  
CW1  
CW2  
AW  
AS  
ns 12  
ns 12  
ns  
Chip enable (CE1) to write end  
Chip enable (CE2) to write end  
Address setup to write end  
Address setup time  
ns 12  
ns  
Write pulse width  
8
9
12  
0
15  
0
17  
0
WP  
AH  
Address hold from end of write  
Data valid to write end  
0
0
ns  
8
9
12  
0
15  
0
15  
0
ns  
DW  
DH  
Data hold time  
0
0
ns 4, 5  
ns 4, 5  
ns 4, 5  
Write enable to output in High Z  
Output active from write end  
WZ  
OW  
3
3
3
3
3
4
AS7C512  
Write waveform 110,11,12  
WE controlled  
t
WC  
t
t
t
AW  
AH  
Address  
WE  
t
WP  
t
AS  
t
DW  
DH  
D
Data Valid  
in  
t
t
WZ  
OW  
D
out  
Write waveform 210,11,12  
CE1 and CE2 controlled  
t
WC  
t
t
AH  
AW  
Address  
t
t
CW1, tCW2  
AS  
CE1  
CE2  
t
WP  
WE  
t
t
t
WZ  
DW  
DH  
D
Data Valid  
in  
D
out  
5
AS7C512  
Typical DC and AC characteristics  
Normalized supply current I , I  
Normalized supply current I , I  
Normalized supply current I  
SB1  
vs. ambient temperature T  
a
CC SB  
CC  
CC SB  
vs. supply voltage V  
vs. ambient temperature T  
a
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
625  
25  
I
V
= 5.0V  
CC  
I
CC  
CC  
5
1
I
I
SB  
SB  
0.2  
0.04  
4.0  
4.5  
5.0  
5.5  
–55  
–10  
35  
80  
-55  
-10  
35  
80  
6.0  
125  
125  
Supply voltage (V)  
Ambient temperature (°C)  
Ambient temperature (°C)  
Normalized access time t  
Normalized access time t  
AA  
Normalized supply current I  
AA  
CC  
vs. supply voltage V  
vs. ambient temperature T  
vs. cycle frequency 1/t , 1/t  
RC WC  
CC  
a
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
T = 25°C  
V
= 5.0V  
V
= 5.0V  
CC  
a
CC  
T = 25°C  
a
4.0  
4.5  
5.0  
5.5  
–55  
–10  
35  
80  
0
20  
40  
60  
6.0  
125  
80  
Supply voltage (V)  
Ambient temperature (°C)  
Cycle frequency (MHz)  
Typical access time change t  
AA  
Output source current I  
Output sink current I  
vs. output voltage V  
OH  
OL  
vs. output voltage V  
vs. output capacitive loading  
OH  
OL  
140  
120  
100  
80  
140  
120  
100  
80  
35  
30  
25  
20  
15  
10  
5
V
= 5.0V  
V
= 5.0V  
V
= 4.5V  
CC  
CC  
CC  
T = 25°C  
T = 25°C  
a
a
60  
60  
40  
40  
20  
20  
0
0.0  
0
0.0  
0
1.25  
2.5  
3.75  
1.25  
2.5  
3.75  
0
250  
500  
750  
5.0  
5.0  
1000  
Output voltage (V)  
Output voltage (V)  
Capacitance (pF)  
6
AS7C512  
Data retention characteristics  
L version only  
Parameter  
Symbol  
Test Conditions  
= 2.0V  
Min  
2.0  
Max  
Unit  
V
V
for data retention  
V
V
CC  
CC  
DR  
Data retention current  
I
t
200  
µA  
ns  
CCDR  
CE1 V –0.2V or  
CC  
Chip deselect to data retention time  
Operation recovery time  
Input leakage current  
0
CE2 0.2V  
CDR  
R
t
t
ns  
RC  
V
V –0.2V or  
CC  
in  
| I |  
1
µA  
V
0.2V  
LI  
in  
Data retention waveform  
L version only  
Data retention mode  
DR 2.0V  
V
4.5V  
4.5V  
V
CC  
t
t
R
CDR  
V
DR  
V
V
CE1  
IH  
IH  
AC test conditions  
– Output load: see Figure B,  
Thevenin equivalent:  
except for t  
and t  
see Figure C.  
CLZ  
CHZ  
168Ω  
D
+1.728V  
out  
– Input pulse level: GND to 3.0V. See Figure A.  
– Input rise and fall times: 5 ns. See Figure A.  
– Input and output timing reference levels: 1.5V.  
+5V  
+5V  
480Ω  
480Ω  
D
D
out  
out  
+3.0V  
90%  
10%  
90%  
10%  
*including scope  
and jig capacitance  
255Ω  
30 pF*  
GND  
255Ω  
5 pF*  
GND  
GND  
Figure B: Output load  
Figure C: Output load for t  
, t  
Figure A: Input waveform  
CLZ CHZ  
Notes  
1. During V power-up, a pull-up resistor to V on CE1 is required to meet I specification.  
CC  
CC  
SB  
2. This parameter is sampled and not 100% tested.  
3. For test conditions, see AC Test Conditions, Figures A, B, C.  
4. t  
and t  
are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.  
CLZ  
CHZ  
5. This parameter is guaranteed but not tested.  
6. WE is HIGH for read cycle.  
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.  
8. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.  
9. All read cycle timings are referenced from the last valid address to the first transitioning address.  
10. CE1 or WE must be HIGH or CE2 LOW during address transitions.  
11. All write cycle timings are referenced from the last valid address to the first transitioning address.  
12. CE1 and CE2 have identical timing.  
7
AS7C512  
Ordering codes  
Package \ Access Time  
12 ns  
15 ns  
20 ns  
25 ns  
35 ns  
AS7C512-12PC  
AS7C512L-12PC  
AS7C512-15PC  
AS7C512L-15PC  
AS7C512-20PC  
AS7C512L-20PC  
AS7C512-25PC  
AS7C512L-25PC  
AS7C512-35PC  
AS7C512L-35PC  
Plastic DIP, 300 mil  
AS7C512-12JC  
AS7C512L-12JC  
AS7C512-15JC  
AS7C512L-15JC  
AS7C512-20JC  
AS7C512L-20JC  
AS7C512-25JC  
AS7C512L-25JC  
AS7C512-35JC  
AS7C512L-35JC  
Plastic SOJ, 300 mil  
Plastic SOIC, 525 mil  
AS7C512-12SC  
AS7C512L-12SC  
AS7C512-15SC  
AS7C512L-15SC  
AS7C512-20SC  
AS7C512L-20SC  
AS7C512-25SC  
AS7C512L-25SC  
AS7C512-35SC  
AS7C512L-35SC  
Part numbering system  
AS7C  
512  
X
–XX  
X
C
Package: P = PDIP 300 mil  
Blank  
L
=
=
Standard power  
Low power  
Commercial temperature range,  
0°C to 70 °C  
SRAM prefix  
Device number  
Access time  
J
= SOJ 300 mil  
S
= SOIC 525 mil  
Representatives, distributors, and sales offices  
DOMESTIC REPS  
KANSAS  
NEW JERSEY  
TEXAS  
EUROPE  
TAIWAN  
Asian Specific Tech.  
+886-2-521-2363  
Britcomp Sales  
Southern States Marketing  
CenTech  
North  
ALABAMA  
(816) 358-8100  
ERA Associates  
(800) 645-5500  
Surrey, England  
+44-1932 347077  
+44-1932 346256  
Austin  
(512) 835-5822  
Concord Component  
(205) 772-8883  
Golden Way Electronics  
+886-2-698-1868 x505  
KENTUCKY  
CC Electro Sales  
(317) 921-5000  
South  
Electro Tech  
(610) 272-2125  
Dallas  
(214) 238-7500  
ARKANSAS  
Southern States Marketing  
(214) 238-7500  
Munich, Germany  
+49-894488496  
Puteam International  
+886-2-729-0373  
Houston  
(713) 895-8533  
LOUISIANA  
Southern States Marketing  
NEW YORK  
Athismons, France  
+33-1-69387678  
CALIFORNIA  
NYC  
UTAH  
Charles Fields & Assoc.  
(801) 299-8228  
North  
Brooks Technical  
(415) 960-3880  
ERA Associates  
(516) 543-0510  
North  
(214) 238-7500  
DISTRIBUTORS  
All American  
HQ: (305) 621-8282  
interACTIVE  
Great Britain, Ireland  
+44-1773-740263  
Upstate  
Tri-Tech  
South  
(713) 895-8533  
LA Area  
Competitive Tech.  
(714) 450-0170  
VERMONT  
Kitchen & Kutchin  
(617) 229-2660  
Axis: Components, Inc.  
HQ: (800) 556-0225  
Rochester  
(716) 385-6500  
Ramtec Int’l B.V.  
MAINE  
Kitchen & Kutchin  
(617) 229-2660  
San Diego  
ATS  
(619) 634-1488  
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Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a  
committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not  
authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion® and the Alliance logo are registered trademarks  
of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.  
ALLIANCE SEMICONDUCTOR  
3099 North First Street San Jose, CA 95134 Tel (408) 383-4900 Fax (408) 383-4999 www.alsc.com  
Printed in U.S.A.  
Copyright © 1996 All rights reserved.  
June 1996  

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