AS80SSTVF16859-64TT [ALSC]
DDR 13-Bit to 26-Bit Registered Buffer; DDR 13位至26位寄存缓冲器
| 型号： | AS80SSTVF16859-64TT |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | DDR 13-Bit to 26-Bit Registered Buffer |
| 文件： | 总13页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2003
Advance Information
PulseC re AS80SSTVF16859
&
DDR 13-Bit to 26-Bit Registered Buffer
Recommended Applications
Features
•
•
•
DDR memory modules: PC1600, PC2100,
PC2700, AND PC3200
Provides complete DDR DIMM logic solution with
PCV857
•
•
•
Differential clock signals
Meets SSTL_2 class II specifications on outputs
Low voltage operation – V = 2.3 V to 2.7 V
DD
•
Available in 64-pin TSSOP and 56-pin VFQFN
packages (MLF2)
SSTL_2-compatible data registers
Block Diagram
Pin Configurations
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
D13
1
2
64
63
CLK
CLKB
3
4
5
62
61
60
D12
VDD
VDDQ
GND
D11
Q1A
Q1B
RESETB
6
7
59
58
VDDQ
GND
Q8A
R
CLK
D1
VREF
8
57
D1
9
56
Q7A
D10
10
11
12
13
55
54
53
52
Q6A
D9
Q5A
GND
D8
Q4A
Q3A
D7
To 12 other channels
Q2A
RESETB
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
51
50
49
48
GND
Q1A
GND
CLKB
CLK
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q7A
Q6A
1
42 D10
D9
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDQ
VDD
VREF
D6
Q5A
D8
Q4A
D7
RESETB
Q3A
GND
D5
D4
Q2A
GND
CLKB
CLK
VDDQ
VDD
VREF
D6
Q8B
Q1A
AS80SSTVF16859
Q7B
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q6B
D3
GND
VDDQ
Q5B
GND
VDDQ
VDD
D2
D5
Q4B
14
29
Q8B
D4
Q3B
D1
Q2B
GND
Q1B
VDDQ
64-Pin TSSOP
6.10 mm body, 0.50 mm pitch
56-Pin VFQFN (MLF2)
8/6/03; v.0.10
Alliance Semiconductor
P. 1 of 13
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AS80SSTVF16859
&
1
Truth Table
Inputs
Q outputs
RESETB
CLK
CLKB
D
Q
L
L
H
H
H
X or floating
X or floating
X or floating
↑
↑
↓
↓
H
L
H
L
2
L or H
L or H
X
Q
0
1 H = high signal level, L = low signal level, ↑ = transition low to high, ↓ = transition high to low, X = don’t care.
2 Output level before the indicated steady state input conditions were established.
Description
The 13-bit to 26-bit PC16859 is a universal bus driver designed for 2.3 V to 2.7 V V operation and SSTL_2 I/O
DD
levels, except for the LVCMOS RESETB input.
Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficient noise margins,
whereas RESETB, an LVCMOS asynchronous signal, is intended for use only at power-up. PC16859 supports
low-power standby operation. A logic level low at RESETB assures that all internal registers and outputs (Q) are
reset to the logic low state, and that all input receivers, data (D), and clock (CLK/CLKB) are switched off. Note that
RESETB must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable
during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held
at a logic low level during power-up.
In the DDR DIMM application, RESETB is specified to be completely asynchronous with respect to CLK and
CLKB, therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power
standby state, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the
time to disable the differential input receivers. This ensures there are no glitches on the output. When coming out
of low power standby state, however, the register will become active quickly relative to the time to enable the
differential input receivers. When the data inputs are at a logic level low and the clock is stable during the low-to-
high transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will
remain at a logic low level.
8/6/03, v.0.10
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P. 2 of 13
AS80SSTVF16859
&
Pin Configuration (64-Pin TSSOP)
Pin number
Pin name
Q(13:1)
GND
Type
Description
1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 20,
21, 22, 23, 24, 25, 28, 29, 30, 31, 32
Output Data output
7, 15, 26, 34, 39, 43, 50, 54, 58, 63
PWR Ground
Output supply voltage, 2.5 V
nominal
6, 18, 27, 33, 38, 47, 59, 64
VDDQ
PWR
35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57, 61, 62
D(13:1)
CLK
CLKB
VDD
Input Data input
48
49
Input Positive master clock input
Input Negative master clock input
PWR Core supply voltage, 2.5 V nominal
Input Reset (active low)
37, 46, 60
51
RESETB
Input reference voltage, 1.25 V
nominal
45
VREF
Input
Pin Configuration (56-Pin MLF2)
Pin number
Pin name
Q(13:1)
GND
Type
Description
1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 18, 19,
20, 21, 22, 50, 51, 52, 53, 54, 56
Output Data output
PWR Ground
37, 48
Output supply voltage, 2.5 V
nominal
9, 17, 23, 27, 34, 44, 49, 55
VDDQ
PWR
24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47
D(13:1)
CLK
CLKB
VDD
Input Data input
35
36
Input Positive master clock input
Input Negative master clock input
PWR Core supply voltage, 2.5 V nominal
Input Reset (active low)
26, 33, 45
38
RESETB
Input reference voltage, 1.25 V
nominal
32
–
VREF
Input
Center
pad
PWR Ground (VFQFN package only)
8/6/03, v.0.10
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P. 3 of 13
AS80SSTVF16859
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Absolute Maximum Ratings
Storage temperature
Supply voltage
- 65° C to +150° C
-0.5 to 3.6 V
1
Input voltage
-0.5 to V + 0.5
DD
1,2
Output voltage
-0.5 to V + 0.5
DD
Input clamp current
± 50 mA
± 50 mA
± 50 mA
± 100 mA
55° C/W
Output clamp current
Continuous output current
V
, V
, or GND current/pin
DDQ
DD
3
Package thermal impedance
1 The input and output negative voltage ratings may be excluded if the input and output clamp ratings are
observed.
2 This current will flow only when the output is in the high state level V0 > VDDQ
.
3 The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only, and functional operation of the device at these or any other conditions
above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions - DDRI / DDR333 (PC1600, PC2100, PC2700)
Guaranteed by design. Not 100% tested in production.
Parameter
Description
Supply voltage
Min
2.3
Typ
2.5
Max
2.7
Units
V
V
DD
V
I/O supply voltage
2.3
2.5
2.7
V
DDQ
V
Reference voltage
1.15
1.25
1.35
V
REF
V
Termination voltage
Input voltage
V
- 0.04
V
V
+ 0.04
REF
V
TT
REF
REF
V
0
V
V
I
DD
V
V
DC input high voltage
AC input high voltage
DC input low voltage
AC input low voltage
Input high voltage level
Input low voltage level
Common mode input range
Differential input voltage
V
V
+ 0.15
V
IH(DC)
IH(AC)
REF
REF
+ 0.31
V
Data
inputs
V
V
V
V
- 0.15
- 0.31
V
IL(DC)
REF
REF
V
IL(AC)
V
1.7
V
IH
RESETB
V
0.7
1.53
V
IL
V
0.97
0.36
V
CLK.
CLKB
ICR
V
V
ID
IX
Cross-point voltage of differential clock
pair
V
(V
/2) - 0.2
(V
/2) + 0.2
DDQ
V
DDQ
I
High-level output current
Low-level output current
Operating free-air temperature
-20
20
mA
mA
° C
OH
I
OL
T
0
70
A
8/6/03, v.0.10
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P. 4 of 13
AS80SSTVF16859
&
Recommended Operation Conditions - DDRI-400 (PC3200)
Guarenteed by design, not 100% tested in production.
Parameter
Description
Min
2.5
Typ
2.6
2.6
1.3
Max
Units
V
V
Supply Voltage
2.7
2.7
DD
V
I/O supply voltage
2.5
V
DDQ
V
Reference voltage
1.25
1.35
V
REF
V
Termination voltage
Input voltage
V
- 0.04
V
V
+ 0.04
REF
V
TT
REF
REF
V
0
V
V
I
DDQ
V
V
DC input high voltage
AC input high voltage
DC input low voltage
AC input low voltage
Input high voltage level
Input low voltage level
Common mode input range
Differential input voltage
V
V
+ 0.15
V
IH(DC)
IH(AC)
REF
REF
+ 0.31
V
Data
Inputs
V
V
V
V
- 0.15
- 0.31
V
IL(DC)
REF
REF
V
IL(AC)
V
1.7
V
IH
RESETB
V
0.7
1.53
V
IL
V
0.97
0.36
V
CLK,
CLKB
ICR
V
V
ID
IX
Cross-point voltage of differential
clock pair
V
(V
/2) - 0.2
(V
/2) + 0.2
DDQ
V
DDQ
I
High-level output current
Low-level output current
Operating free-air temperature
-16
16
70
mA
mA
° C
OH
I
OL
T
0
A
8/6/03, v.0.10
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P. 5 of 13
AS80SSTVF16859
&
DC Electrical Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
TA = 0° C to 70° C, V = 2.5 ± 0.2 V, and V
= 2.5 ± 0.2 V (unless otherwise stated)
DD
DDQ
Guaranteed by design. Not 100% tested in production..
Symbol
Parameters
Test conditions
I = -18 mA
VDD
Min
Typ
Max
Units
V
2.3 V
-1.2
V
IK
I
2.3 V to
2.7 V
V
0.2
-
DD
I
= -100 µA
= -16 mA
= 100 µA
= 16 mA
V
V
V
OH
V
OH
I
2.3 V
1.95
OH
2.3 V to
2.7 V
I
0.2
OL
V
OL
I
2.3 V
2.7 V
2.7 V
0.35
± 5
V
OL
I
All inputs
V = V or GND
µA
µA
I
I
DD
Standby (static)
RESETB = GND
0.01
I
Operating
(static)
V = V
or V
,
DD
I
IH(AC)
IL(AC)
DD
2.7 V
25
mA
RESETB = V
RESETB = V
,
DD
Dynamic
operating (clock
only)
µA/
clock
MHz
V = V
or V
,
I
IH(AC)
IL(AC)
2.7 V
30
10
CLK and CLKB switching
50% duty cycle
I = 0
O
RESETB = V
,
DD
V = V
or V
,
I
I
IH(AC)
IL(AC)
µΑ/
clock
MHz/
data
input
DDD
CLK and CLKB = switching
50% duty cycle
Dynamic
operating (per
each data input)
2.7 V
One data input switching at
half clock frequency, 50% duty
cycle
2.3 V to
2.7 V
r
Output high
Output low
I
= -20 mA
= 20 mA
7
7
20
20
4
Ω
Ω
Ω
OH
OH
2.3 V to
2.7 V
r
I
OL
OL
|r - r | each
OH
OL
r
I = 20 mA, T = 25° C
2.5 V
O(D)
O
A
separate bit
Data inputs
V = V
± 310 mV,
REF
2.5 V
2.5 V
2.5V
2.5
2.5
2.5
3.5
3.5
3.5
pF
pF
pF
I
V
= 1.25 V,
= 360 mV
ICR
C
CLK and CLKB
RESETB
i
V
I(PP)
V = V or GND
I
DD
8/6/03, v.0.10
Alliance Semiconductor
P. 6 of 13
AS80SSTVF16859
&
DC Electrical Characteristics - DDRI-400 (PC3200)
TA = 0° C to 70° C, V = 2.6 ± 0.1 V, and V
= 2.6 ± 0.1 V (unless otherwise stated)
DD
DDQ
Guaranteed by design. Not 100% tested in production..
Symbol
Parameters
Test conditions
I = -18 mA
VDD
Min
Typ
Max
Units
V
2.5 V
-1.2
V
IK
I
2.5 V to
2.7 V
V
0.2
-
DD
I
= -100 µA
V
V
V
OH
V
OH
I
= -8 mA
2.5 V
1.95
OH
2.5 V to
2.7 V
I
= 100 µA
0.2
OL
V
OL
I
= 8 mA
2.5 V
2.7 V
2.7 V
0.35
± 5
V
OL
I
All inputs
V = V or GND
µA
µA
I
I
DD
Standby (static)
RESETB = GND
0.01
I
Operating
(static)
V = V
or V
,
DD
I
IH(AC)
IL(AC)
DD
2.7 V
25
mA
RESETB = V
RESETB = V
,
DD
Dynamic
operating (clock
only)
µA/
clock
MHz
V = V
or V
,
I
IH(AC)
IL(AC)
2.7 V
30
10
CLK and CLKB switching
50% duty cycle
I = 0
O
RESETB = V
,
DD
V = V
or V
,
I
I
IH(AC)
IL(AC)
µΑ/
clock
MHz/
data
input
DDD
CLK and CLKB = switching
50% duty cycle
Dynamic
operating (per
each data input)
2.7 V
One data input switching at
half clock frequency, 50% duty
cycle
2.5 V to
2.7 V
r
Output high
Output low
I
= -16 mA
= 16 mA
7
7
20
20
4
Ω
Ω
Ω
OH
OH
2.5 V to
2.7 V
r
I
OL
OL
|r - r | each
OH
OL
r
I = 20 mA, T = 25° C
2.6 V
O(D)
O
A
separate bit
Data inputs
V = V
± 310 mV,
REF
2.6 V
2.6 V
2.6V
2.5
2.5
2.5
3.5
3.5
3.5
pF
pF
pF
I
V
= 1.25 V,
= 360 mV
ICR
C
CLK and CLKB
RESETB
i
V
I(PP)
V = V or GND
I
DD
8/6/03, v.0.10
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P. 7 of 13
AS80SSTVF16859
&
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted.)
Guaranteed by design. Not 100% tested in production
* This parameter is not necessarily production tested..
Units
VDDQ = 2.5V±0.2V VDDQ = 2.6V±0.1V
Symbol
Parameters
Min
Max
Min
Max
f
Clock frequency
200
270
MHz
ns
CLOCK
t
Pulse duration, CK, CKLB high or low
2.5
2.5
W
1
tACT
*
Differential inputs active time
22
22
22
22
ns
2
tINACT
*
Differential inputs inactive time
ns
3,5
Setup time, fast slew rate
Setup time, slow slew rate
0.75
0.9
0.4
0.6
0.4
0.6
ns
Data before CLK↑,
CLKB↓
t
S
4,5
3,5
ns
ns
Hold time, fast slew rate
0.75
0.9
Data after CLK↑,
CLKB↓
t
h
4,5
Hold time, slow slew rate
ns
1 Data inputs must be low a minimum time of tACT max, after RESETB is taken high
2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESETB is taken low
3 For data signal input slew rate > 1 V/ns
4 For data signal input slew rte > 0.5 V/ns and < 1 V/ns
5 CLK, CLKB signals iput slew rates are > 1 V/ns
Switching Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
(Over recommended operating free-air temperature range unless otherwise noted.)
VDD = 2.5 V ± 0.2 V
Symbol
From (input)
To (output)
Min
200
1.1
1.1
–
Typ
Max
–
Units
MHz
ns
f
–
max
CLK, CLKB (TSSOP)
CLK, CLKB (VFQFN[MLF2])
RESETB
Q
Q
Q
2.8
2.8
5.0
t
PD
ns
t
–
ns
phl
Switching Characteristics - DDRI-400 (PC3200)
(Over recommended operating free-air temperature range unless otherwise noted.)
VDD = 2.6 V ± 0.1 V
Min Typ Max
Symbol
From (input)
To (output)
Units
MHz
ns
f
210
1.1
max
t
Q
Q
Q
2.2
2.48
3.5
CLK, CLKB (VFQFN[MLF2])
Simultaneous switching
PD
t
ns
PDSS
t
RESETB
ns
phl
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P. 8 of 13
AS80SSTVF16859
&
Parameter Measurement Information (V = 2.5 V ± 0.2 V)
DD
V
TT
R = 50 Ω
L
From output under test
Test point
1
C = 30 pF
L
Load circuit
1
C includes probe and jig capacitance.
L
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, Z = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified).
o
The outputs are measured one at a time with one transition per measurement.
V
V
= V
= V
/2.
TT
IH
REF
REF
REF
DDQ
= V
+ 310 mV (AC voltage levels) for differential inputs. V = V for LVCMOS input.
IH DD
V = V
- 310 mV (AC voltage levels) for differential inputs. V = GND for LVCMOS input.
IL
IL
t
and t
are the same as t .
PLH
PHL pd
Input active and inactive times
VDD
LVCMOS RESETB
Input
VDD/2
tinact
VDD/2
tact
0 V
1
IDD
IDDH
90%
10%
IDDL
1 IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Pulse duration
t
w
V
V
IH
IL
V
V
REF
Input
REF
Setup and hold times
V
I(pp)
V
Timing input
Input
ICR
t
t
h
s
V
V
IH
IL
V
V
REF
REF
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P. 9 of 13
AS80SSTVF16859
&
Propagation delay times
V
I(pp)
V
V
ICR
Timing input
ICR
t
t
PHL
PLH
V
V
OH
OL
V
V
TT
TT
Output
LVCMOS RESETB
Input
V
IH
IL
V
/2
DD
V
t
PHL
Output
V
V
OH
OL
V
TT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
LOW-TO-HIGH SLEW RATE MEASUREMENT
VOH
dt_r
dV_r
80%
VOH
Output
80%
20%
dt_f
VOL
Output
dV_f
20%
VOL
Output slew rates over recommended operating free-air temperature range (unless otherwise noted)
V
= 2.5 V + 0.2V *
V
= 2.6 V + 0.1 V *
CC
CC
Parameter
dV/dt_r
From
20%
80%
To
Min
1
Max
Min
1
Max
Unit
V/ns
V/ns
V/ns
80%
20%
4
4
1
4
4
1
dV/dt_f
1
1
dV/dt_∆
20% or 80% 80% or 20%
*For this test condition, VDDQ is always equal to VDD
**Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
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P. 10 of 13
AS80SSTVF16859
&
Package Dimensions (64- Pin TSSOP)
Millimeters
Min Max
Inches
c
Symbol
Min
–
Max
N
L
A
A1
A2
b
–
1.20
0.15
1.05
0.27
0.20
0.047
0.006
0.041
0.011
0.008
0.05
0.80
0.17
0.09
0.002
0.32
E1
E
0,007
0.0035
c
Index area
D
See variations below
8.10 basic 0.319 basic
E
1
2
D
E1
e
6.00
6.20
0.236
0.244
α
0.50 basic
0.020 basic
A2
A
Seating plane
L
0.45
0.75
0.018
0.030
A1
N
See variations below
aaa C
e
b
α
0°
8°
0°
8°
aaa
–
0.10
–
0.004
6.10 mm (240 mil) body,
0.50 mm (0.020 mil) pitch TSSOP
Variations:
D (mm)
D (inch)
N
Min
Max
Min
Max
64
16.90
17.10
0.665
0.673
8/6/03, v.0.10
Alliance Semiconductor
P. 11 of 13
AS80SSTVF16859
&
Package Dimensions (56-Pin MLF2)
0.25 C A
Common dimensions
D
A
Symbol
Min
Typ
Max
1.00
0.05
0.80
D/2
A2
A1
A3
D1
A
A1
A2
A3
D
0.85
D1/2
0.25 C B
0.00
0.01
0.65
0.18 Dia.
0.20 BSC
8.00 BSC
7.75 BSC
8.00 BSC
7.75 BSC
E1
E
D1
E
E1/2 E/2
E1
θ
12
θ
0.20 C B
0.20 C A
P
0.24
0.13
0.42
0.17
0.60
0.23
Seating plane
R
Top view
Side view
Pitch variation D
e
N
0.50 BSC
56
14
14
Nd
Ne
L
0.25 C A B
D2/2
4x P
D2
Pin ID
0.30
0.18
0.00
4.35
5.05
0.40
0.23
0.20
4.50
5.20
0.50
0.30
0.45
4.65
5.35
4x P
b
Q
0.35
D2
E2
(Ne - 1) X e
E2
E2/2
L
e
(Nd - 1) X e
b
A1
Bottom view
Terminal tip
For odd terminal/side For even terminal/side
Cross section
8/6/03, v.0.10
Alliance Semiconductor
P. 12 of 13
AS80SSTVF16859
&
Ordering Information
Ordering Number
Marking
Package
Qty per Reel Temperature
AS80SSTVF16859-64TT
AS80SSTVF16859T
64-Pin TSSOP, Tube
0°C to 70°C
64-Pin TSSOP,
Tape & Reel
AS80SSTVF16859-64TR
AS80SSTVF16859-56KT
AS80SSTVF16859-56KR
AS80SSTVF16859T
AS80SSTVF16859K
AS80SSTVF16859K
2500
2500
0°C to 70°C
0°C to 70°C
0°C to 70°C
56-pin MLF2, Tube
56-pin MLF2,
Tape & Reel
8/6/03; v.0.10
Alliance Semiconductor
P. 13 of 13
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