AS8C801800 [ALSC]

Power down controlled by ZZ input;


型号：	AS8C801800
厂家：	ALLIANCE SEMICONDUCTOR CORPORATION
描述：	Power down controlled by ZZ input
文件：	总18页 (文件大小：8296K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

256K X 36, 512K X 18

3.3VSynchronousSRAMs

3.3V I/O, Burst Counter

AS8C803600

AS8C801800

PipelinedOutputs,SingleCycleDeselect

Features

256K x 36 / 512K x 18. The SRAMs contain write, data,

◆

256K x 36, 512K x 18 memory configurations

Supports high system speed:

address and control registers. Internal logic allows the SRAM to

generate aself-timed writebaseduponadecision whichcanbeleft

until the endofthe write cycle.

◆

– 150MHz 3.8ns clock access time

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,asthe AS8C803600/801800 canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

andthe LBO inputpin.

◆

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O supply (VDDQ)

◆

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack (TQFP)

The AS8C803600/801800 SRAMs utilize the latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm100-

pin thinplasticquadflatpack(TQFP),

Description

The AS8C803600/801800 are high-speed SRAMs organized as

Pin Description Summary

-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

0, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

, BW

, BW ⁽¹⁾

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

NOTE:

5310 tbl 01

1. BW3 and BW4 are not applicable for other devices

September 2010

AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial Temperature Range

(1)

Pin Definitions

Symbol

Pin Function

I/O

Active

Description

A0-A18

Address Inputs

N/A

Synchronous Address inputs. The address register is triggered by a combination of the

rising edge of CLK and ADSC Low or ADSP Low and CE Low.

Address Status

LOW

Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is

ADSC

ADSP

ADV

(Cache Controller)

used to load the address registers with new addresses.

Address Status

(Processor)

Synchronous Address Status from Processor. ADSP is an active LOWinput that is used to

load the address registers with new addresses. ADSP is gated by CE.

Burst Address

Advance

Synchronous Address Advance. ADV is an active LOW input that is used to advance the

internal burst counter, controlling burst access after the initial address is loaded. When the

inputis HIGH the burst counter is not incremented; that is, there is no address advance.

Byte Write Enable

LOW

Synchronous byte write enable gates the byte write inputs BW

-BW . If BWE is LOW at the

BWE

rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is

HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.

Individual Byte

Write Enables

LOW

N/A

Synchronous byte write enables. BW

controls I/O0-7, I/OP1, BW

controls I/O8-15, I/OP2, etc.

-BW

Any active byte write causes all outputs to be disabled.

Chip Enable

Synchronous chip enable. CE is used with CS

CE also gates ADSP.

and CS1 to enable the IDT71V67603/7803.

CLK

Clock

This is the clock input. All timing references for the device are made with respect to this

input.

Chip Select 0

Chip Select 1

HIGH

LOW

Synchronous active HIGH chip select. CS

Synchronous active LOW chip select. CS

is used with CE and CS

to enable the chip.

is used with CE and CS0 to enable the chip.

Global Write

Enable

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK. GW supersedes individual byte write enables.

I/O

I/OP1-I/OP4

-I/O31

Data Input/Output

I/O

N/A

Synchronous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

Linear Burst Order

LOW

Asynchronous burstorder selection input. When LBO is HIGH, the interleaved burst

sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a

static input and must not change state while the device is operating.

LBO

Output Enable

LOW

Asynchronous output enable. When OE is LOW the data outputdrivers are enabled on the

I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-

impedance state.

DDQ

Power Supply

Ground

N/A

3.3V core power supply.

3.3V I/O Supply.

N/A

Ground.

No Connect

Sleep Mode

N/A

NC pins are not electrically connected to the device.

HIGH

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

AS8C803600/1800 to its lowest power consumption level. Data retention is guaranteed in

Sleep Mode.

5310 tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial Temperature Range

Functional Block Diagram

LBO

ADV

INTERNAL

ADDRESS

Burst

Sequence

CEN

256K x 36/

CLK

Burst

Logic

18/19

Binary

Counter

512K x 18-

ADSC

A0*

BIT

CLR

MEMORY

A1*

ADSP

ARRAY

CLK EN

A0,A1

A2–A18

A0–A17/18

ADDRESS

36/18

18/19

Byte 1

Write Register

BWE

Byte 1

Write Driver

Byte 2

Write Register

Byte 2

Write Driver

BW2

Byte 3

Write Register

Byte 3

Write Driver

Byte 4

Write Register

Byte 4

Write Driver

BW4

OUTPUT

Enable

DATA INPUT

CLK EN

Powerdown

Enable

Delay

OUTPUT

BUFFER

36/18

I/O

0–I/O31

I/OP1–I/OP4

5301 drw 01

6.42

AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial Temperature Range

(1)

Absolute Maximum Ratings

Recommended Operating

Temperature and Supply Voltage

Symbol

Rating

Commercial

Unit

Grade

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

VDDQ

(2)

TERM

Terminal Voltage with

Respect to GND

-0.5 to +4.6

Commercial

Industrial

3.3V±5%

(3,6)

(4,6)

(5,6)

TERM

Terminal Voltage with

Respect to GND

-0.5 to VDD

-0.5 to VDD +0.5

-0.5 to VDDQ +0.5

-0 to +70

3.3V±5%

5310 tbl 04

NOTE:

1. TA is the "instant on" case temperature.

VTERM

Terminal Voltage with

Respect to GND

Recommended DC Operating

VTERM

Terminal Voltage with

Respect to GND

Conditions

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Min. Typ.

3.135 3.3

Max.

Unit

^oC

T ⁽⁷⁾

Operating Temperature

DDQ

3.465

Temperature

Under Bias

-55 to +125

TBIAS

2.0

Storage

-55 to +125

TSTG

____

Input High Voltage - Inputs

Input High Voltage -I/O

Input Low Voltage

VDD +0.3

Temperature

____

2.0

VDDQ +0.3

Power Dissipation

DC Output Current

2.0

-0.3⁽¹⁾

0.8

IOUT

5310 tbl 05

5310 tbl 03

NOTES:

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

165 fBGA Capacitance

100 Pin TQFP Ca pacitance

(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

Max. Unit

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

Max. Unit

Symbol

CIN

CI/O

VOUT = 3dV

CI/O

VOUT = 3dV

5310 tbl 07

5310 tbl 07b

119 BGA Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

CIN

CI/O

5310 tbl 07a

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 256K x 36, 100-Pin TQFP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/OP3

I/O16

I/O17

I/OP2

I/O15

I/O14

VDDQ

VSS

I/O18

I/O19

I/O20

I/O21

I/O13

I/O12

I/O11

I/O10

VSS

VDDQ

I/O22

I/O23

I/O9

I/O8

DD / NC⁽¹⁾

VDD

ZZ⁽²⁾

I/O24

I/O25

I/O7

I/O6

VDDQ

DDQ

VSS

I/O26

I/O27

I/O28

I/O29

I/O

VSS

VDDQ

I/O30

I/O31

I/OP4

I/O

I/OP1

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5301 drw 02

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 512K x 18, 100-Pin TQFP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DDQ

VDDQ

VSS

I/O8

I/OP1

I/O

I/O9

I/O

VSS

DDQ

VDDQ

I/O10

I/O11

I/O

DD / NC⁽¹⁾

VSS

VDD

ZZ⁽²⁾

I/O12

I/O13

I/O

DDQ

VSS

I/O14

I/O15

I/OP2

I/O

VSS

DDQ

VDDQ

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5310 drw 03

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial Temperature Range

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(VDD = 3.3V ± 5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

VDD = Max., VIN = 0V to VDD

µA

(1)

___

ZZ and LBO Input Leakage Current

Output Leakage Current

Output Low Voltage

|I^LZZ

DD = Max., VIN = 0V to VDD

OUT = 0V to VDDQ, Device Deselected

OL = +8mA, VDD = Min.

OH = -8mA, VDD = Min.

µA

|I^LO

VOL

0.4

___

VOH

Output High Voltage

2.4

5310 tbl 08

NOTE:

1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.

DC Electrical Characteristics Over the Operating

(1)

Temperature and SupplyVoltage Range

166MHz

150MHz

Com'l

133MHz

Com'l

Unit

Symbol

Parameter

Test Conditions

Com'l only

Ind

Operating Power Supply

Current

Device Selected, Outputs Open, VDD = Max.,

340

305

325

260

280

(2)

VDDQ = Max., VIN > VIH or < VIL, f = fMAX

ISB1

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

DDQ = Max., VIN > VHD or < VLD, f = 0^(2,3)

175

170

ISB2

Clock Running Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

160

155

150

(2,3)

DDQ = Max., VIN > VHD or < VLD, f = fMAX

ZZ > VHD, DD = Max.

Full Sleep Mode Supply

Current

IZZ

5310 tbl 09

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

DDQ/2

AC Test Conditions

AC Test Load

(VDDQ = 3.3V)

50Ω

Input Pulse Levels

0 to 3V

2ns

I/O

Z0 = 50Ω

Input Rise/Fall Times

5310 drw 06

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

1.5V

Figure 1. AC Test Load

1.5V

See Figure 1

5310 tbl 10

∆tCD

(Typical, ns)

20 30 50

80 100

Capacitance (pF)

200

5310 drw 07

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial Temperature Range

Synchronous Truth Table^(1,3)

Operation

Address

Used

CS0

CLK

I/O

ADSP ADSC ADV

BWE

BWx

(2)

Deselected Cycle, Power Down

Read Cycle, Begin Burst

None

HI-Z

None

External

DOUT

Read Cycle, Begin Burst

HI-Z

Read Cycle, Begin Burst

DOUT

Read Cycle, Begin Burst

DOUT

Read Cycle, Begin Burst

HI-Z

Write Cycle, Begin Burst

OUT

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

OUT

Current

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

5310 tbl 11

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

6.42

AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial Temperature Range

SynchronousWrite Function Truth Table^{(1, 2)}

Operation

BWE

BW4

Read

Write all Bytes

Write Byte 1⁽³⁾

Write Byte 2⁽³⁾

Write Byte 3⁽³⁾

Write Byte 4⁽³⁾

5310 tbl 12

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. BW³and BW4 are not applicable other devices

3. Multiple bytes may be selected during the same cycle.

Asynchronous Truth Table⁽¹⁾

Operation⁽²⁾

I/O Status

Power

Read

Data Out

High-Z

Active

Read

Write

High-Z – Data In

High-Z

Active

Deselected

Sleep Mode

Standby

Sleep

High-Z

5310 tbl 13

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

Interleaved Burst SequenceTable (LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

5310 tbl 14

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

Linear Burst Sequence Table (LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

5310 tbl 15

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial Temperature Range

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

166MHz

150MHz

133MHz

Max.

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Unit

____

CY C

Clock Cycle Time

6.7

2.6

7.5

(1)

Clock High Pulse Width

Clock Low Pulse Width

2.4

tCH

____

(1)

tCL

Output Parameters

____

Clock High to Valid Data

Clock High to Data Change

Clock High to Output Active

3.5

3.8

4.2

____

tCDC

1.5

(2)

CL Z

____

(2)

Clock High to Data High-Z

1.5

3.5

1.5

3.8

1.5

4.2

CHZ

____

tOE

Output Enable Access Time

3.5

3.8

4.2

____

(2)

Output Enable Low to Output Active

Output Enable High to Output High-Z

OLZ

____

3.5

3.8

4.2

OHZ

Set Up Times

____

SAV

Address Setup Time

1.5

Address Status Setup Time

Data In Setup Time

Write Setup Time

Address Advance Setup Time

Chip Enable/Select Setup Time

Hold Times

____

HAV

Address Hold Time

0.5

Address Status Hold Time

Data In Hold Time

Write Hold Time

Address Advance Hold Time

Chip Enable/Select Hold Time

Sleep Mode and Configuration Parameters

____

ZZPW

ZZ Pulse Width

100

(3)

ZZR

ZZ Recovery Time

Configuration Set-up Time

____

(4)

CFG

5310 tbl 16

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

6.42

AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial Temperature Range

100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline

6.17

ORDERING INFORMATION

VCC

Range

Speed

Mhz

Alliance

Organization

Package

Operating Temp

AS8C803600-QC150N

AS8C801800-QC150N

256K x 36

512K x 18

3.1 - 3.4V

100 pin TQFP

Comercial: 0 - 70C

150

PART NUMBERING SYSTEM

Device

Conf.

Mode

Package

Q = 100 Pin TQFP

Operating Temp

0 ~ 70C

AS8C

Speed

01= ZBT

00 = Pipelined

25 = Flow- Thru

150MHz N= Leadfree

Sync.

SRAM prefix

18= x18

36 = x36

80 = 8M

Organiza it on

512K 16

Package

Operat

44pin

Indust

AS6C

8016

evi x1ec 6

-5

mber

Roc

Lea

owe

Alliance Memory, Inc.

551 Taylor way, suite#1,

San Carlos, CA 94070

Tel: 650-610-6800

Part Number: AS8C803600/801800

Document Version: v. 1.0

Fax: 650-620-9211

www.alliancememory.com

Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this

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contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any

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claims arising from such use.

618.42

AS8C801800 [ALSC]

相关型号：

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AS8E128K32N-120/IT

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