AS9C25512M2018L-250FC [ALSC]
2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface; 2.5V 512 / 256K ×18同步双端口SRAM与3.3V或2.5V的接口
| 型号： | AS9C25512M2018L-250FC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| 文件： | 总30页 (文件大小：1101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2004
Preliminary Information
AS9C25512M2018L
AS9C25256M2018L
®
2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
Features
•
Dual Chip enables on both ports for easy
depth expansion
•
True Dual-Port memory cells that allow simulta-
neous access of the same memory location
•
•
•
Interrupt and Collision Detection Features
2.5 V power supply for the core
LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
Snooze modes for each port for standby
operation
15mA typical standby current in power
down mode
Available in 256-pin Ball Grid Array
(BGA), 144-pin Thin Quad Flatpack
(TQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
[1]
•
•
Organisation: 524,288/262,144 × 18
Fully Synchronous, independent operation on
both ports
•
•
•
Selectable Pipeline or Flow-Through output
mode
Fast clock speeds in Pipeline output mode: 250
MHz operation (9Gbps bandwidth)
Fast clock to data access: 2.8ns for Pipeline out-
put mode
•
•
•
•
•
•
Asynchronous output enable control
Fast OE access times: 2.8ns
Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
•
Supports JTAG features compliant with
IEEE 1149.1
[1]
•
19/18 -bit counter with Increment, Hold and
Repeat features on each port
Note:
1. AS9C25512M2018L/AS9C25256M2018L
Selection guide
Feature
-250
4
-200
5
-166
6
-133
7.5
133
4.2
83
Units
ns
Minimum cycle time
Maximum Pipeline clock frequency
Maximum Pipeline clock access time
Maximum flow-through clock frequency
Maximum flow-through clock access time
Maximum operating current
250
2.8
150
6.5
TBD
18
200
3.4
133
7.5
350
18
166
3.6
100
10
MHz
ns
MHz
ns
12
300
18
260
18
mA
mA
Maximum snooze mode current
9/24/04; v.1.2
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Copyright © Alliance Semiconductor. All rights reserved.
AS9C25512M2018L
AS9C25256M2018L
®
Dual port logic block diagram
R/W Control
R/W Control
BE1 -BE0
BE1 -BE0
B B
A
A
REGISTER BANK
REGISTER BANK
REGISTER BANK
REGISTER BANK
D
D
D
D
Q
Q
Q
Q
CE0
CE0
A
B
CE1
CE1
A
B
R/W
R/W
B
A
O/P Control
O/P Control
O/P Control
O/P Control
PL/FT
PL/FT
PL/FT
PL/FT
B
A
Qout <17:0>
B
Qout <17:0>
A
OE
OE
B
A
0
1
0
1
REGISTER BANK
REGISTER BANK
D
D
Q
Q
True Dual Port
Memory Array
512/256K X 18
REGISTER BANK
REGISTER BANK
DQ17 -DQ0
DQ17 -DQ0
B B
D
D
A
A
Q
Din <17:0>
A
Q
Din <17:0>
B
RPT
RPT
B
A
A
A
ADS
INC
ADS
B
INC
B
Address
Address
Decoding
Decoding
[1]
[1]
-A0
B
A18
-A0
A18
A
A
B
REGISTER BANK
REGISTER BANK
Increment
Logic
Increment
Logic
D
D
Q
Q
Mirror
Mirror
Register
Register
Address Counter A
Address Counter B
CE0
CE1
CE0
CE1
A
A
B
OPT
OPT
B
Interrupt/Collision
A
B
Detection
R/W
R/W
B
CLK
A
CLK
B
A
PL/FT
Logic/Registers
PL/FT
B
A
CLK
CLK
A
B
B
OPT
OPT
A
INT
INT
B
A
COL
COL
B
A
Snooze
Logic
Snooze
Logic
ZZ
ZZ
B
A
TCK
TMS
TRST
TDI
JTAG
TDO
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
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AS9C25512M2018L
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®
General Description
The AS9C25512M2018L/AS9C25256M2018L is a high-speed CMOS 9/4.5-Mbit synchronous Dual-Port Static Random Access Memory
device, organized as 524,288/262,144 × 18 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clock-
to-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation.
Each port contains a 19/18 bit linear burst counter on the input address register that can loop through the whole address sequence. After
externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or
the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control,
data, and address inputs provide minimal setup and hold times.
The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write
to a certain location while another port is reading from the same location, but the validity of read data is not guaranteed. However, the
reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than
one port at the same time is undefined.
The Asynchronous Output Enable input pin allows asynchronous disabling of output buffers at any given time. The Byte Enable inputs
allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1,
permits the on-chip circuitry of each port to enter a very low standby power mode.
AS9C25512M2018L/AS9C25256M2018L can support an operating voltage of either 3.3V or 2.5V on either or both ports, which is
controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. This device is available in 256-pin Ball Grid
Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 144-pin Thin Quad Flatpack (TQFP)
Address Counter
The AS9C25512M2018L/AS9C25256M2018L carries an internal 19/18 bit address counter for each port which can loop through the entire
memory array. The Address counter features are discussed below:
Load: Any required external address can be loaded on to the counter. This feature is similar to normal address load in conventional
memories.
Increment: The address counter has the capability to internally increment the address value, potentially covering the entire memory array.
Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known
location has to be loaded before Increment operation.
Hold: The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs.
Repeat: The previously loaded address (loaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 19/18
bit register called “Mirror register” is used to hold the last loaded address.This register is not initialized on Power-up, hence a known
location has to be loaded before Repeat operation (Refer Counter control truth table for details).
9/24/04, v.1.2
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AS9C25512M2018L
AS9C25256M2018L
®
Ball Assignment - 256-ball BGA
AS9C25512M2018L/AS9C25256M2018L
B - 256
Top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
NC
TDI
NC
A17
A14
A11
A8
NC
CE1
OE
INC
A5
A4
A6
A2
A1
A3
A0
A
NC
NC
A
B
C
D
E
F
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
[1]
INT
NC
TDO
VSS
NC
A15
A13
A12
A10
A9
A7
BE1
CE0
BE0
R/W
RPT
A
VDD
NC
NC
NC
DQ8
DQ8
DQ7
DQ6
NC
A
A18
A
A
A
COL
NC
DQ9
A16
NC
CLK
ADS
OPT
A
A
A
B
A
A
A
A
B
B
A
DQ9
PL/FT VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
B
VDD
NC
NC
NC
A
A
A
B
B
A
A
B
DQ10 DQ10
NC VDDQ
VDD
VDD
VSS
VSS
VDD
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD VDDQ
VDD VDDQ
VSS VDDQ
VSS VDDQ
DQ7
B
A
A
A
B
B
A
A
B
B
B
B
A
A
B
B
A
A
A
DQ11
NC
NC
NC
DQ11 VDDQ
DQ6
DQ5
NC
NC
A
B
B
G
H
J
DQ12 VDDQ
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
NC
NC
G
H
J
A
A
NC
DQ12
NC
VDDQ
NC
DQ5
DQ4
DQ3
DQ2
NC
B
B
A
A
B
DQ13 DQ14 DQ13 VDDQ
ZZ
ZZ
VDDQ
DQ4
NC
DQ3
NC
A
B
B
B
A
B
B
K
L
M
N
P
NC
NC
NC
DQ14 VDDQ
VSS
VDD
VDD
VSS VDDQ
VDD VDDQ
VDD VDDQ
K
L
M
N
P
A
DQ15
DQ15 VDDQ
DQ2
DQ1
NC
NC
A
B
A
DQ16 DQ16
NC
NC
VDDQ
VDD
NC
DQ1
DQ0
NC
B
A
B
A
B
A
NC
DQ17
DQ17
NC
PL/FT VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
A
VDD
NC
B
B
B
A
A
B
B
A
B
COL
TMS
TRST
NC
A16
A13
A15
A14
A10
A12
A11
A7
A9
A8
NC
BE0
CE0
CE1
CLK
ADS
A6
A4
A5
A3
A1
A2
NC
DQ0
NC
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A
[1]
R
T
INT
BE1
R/W
RPT
INC
OPT
NC
R
T
B
A18
B
B
B
B
B
B
NC
1
TCK
2
A17
NC
8
OE
A0
B
NC
NC
B
B
3
4
5
6
7
9
10
11
12
13
14
15
16
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
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AS9C25512M2018L
AS9C25256M2018L
®
Ball Assignment - 208-ball fpBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
B
C
D
E
F
DQ9
INT
VSS
TDO
NC
A16
A12
A8
NC
VDD CLK
INC
A4
A1
A2
A0
OPT
A
NC
VSS
A
B
C
D
E
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
NC
VSS
COL
TDI
A17
A13
A14
A11
A9
NC
CE0
CE1
VSS
VSS
ADS
A5
A6
A3
NC VDDQ DQ8
NC
A
A
A
A
A
B
A
[1]
VDDQ DQ9 VDDQ PL/FT
A10
BE1
BE0
R/W
VDD DQ8
B
NC
VSS
A
B
B
A A18
A
A
A
A
A
A
NC
VSS DQ10
NC
A15
A7
VDD
OE
RPT
VDD
NC VDDQ DQ7
DQ7
NC
A
A
A
A
A
A
A
A
B
DQ11
NC VDDQ DQ10
DQ6
A
NC
VSS
A
B
B
VDDQ DQ11
NC
VSS
NC
VSS
DQ6
NC VDDQ
F
A
B
B
B
B
B
B
G
H
J
NC
VSS DQ12
NC VDDQ DQ5
A
NC
G
H
J
A
A
VDD
NC VDDQ DQ12
VDD
NC
VSS
DQ5
B
B
B
AS9C25512M2018L/AS9C25256M2018L
VDDQ VDD
VSS
ZZ
ZZ
A
VDD
VSS VDDQ
A
B
F - 208
Top view
K
L
M
N
P
DQ14
NC
VSS DQ13
VSS
DQ3 VDDQ DQ4
B
VSS
K
L
B
B
B
A
DQ14 VDDQ DQ13
NC
DQ3
NC
VSS
DQ4
A
A
B
A
A
A
VDDQ
NC
NC
DQ15
NC
VSS
VSS
DQ2 VDDQ
M
N
P
A
B
B
VSS
DQ15
DQ1 VDDQ
NC
DQ2
NC
B
A
A
DQ16 DQ16 VDDQ COL
TRST A16
A12
A8
NC
VDD CLK
INC
A4
A1
A2
A0
NC
DQ1
A
VSS
B
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
R
T
U
VSS
NC
NC
DQ17
TCK
A17
A13
A14
A11
A9
NC
CE0
CE1
VSS
VSS
ADS
A5
A6
NC VDDQ DQ0 VDDQ
R
T
B
B
B
B
B
B
A
B
[1]
DQ17 VDDQ
TMS
NC
A10
BE1
BE0
R/W
VSS
NC
VSS
NC
A
A
B
A18
B
B
B
B
VSS
INT
PL/FT
3
A15
A7
7
VDD
9
OE
RPT
11
A3B
12
VDD OPT
NC
16
DQ0
A
U
B
B
B
B
B
1
2
4
5
6
8
10
13
14
15
17
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
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®
Pin Assignment - 144-pin TQFP
VSS
VDDQB
VSS
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
OPTA
VDDQB
VSS
DQ8A
DQ8B
DQ7A
DQ7B
DQ6A
DQ6B
VSS
VDDQA
DQ5A
DQ5B
VSS
VDDQB
VDD
DQ9A
DQ9B
DQ10A
DQ10B
DQ11A
DQ11B
VDDQA
VSS
DQ12A
DQ12B
VDDQB
ZZB
VDD
VDD
VSS
VSS
VDDQA
VSS
DQ13B
DQ13A
DQ14B
DQ14A
VDDQB
VSS
DQ15B
DQ15A
DQ16B
DQ16A
DQ17B
DQ17A
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VDD
VSS
VSS
ZZA
AS9C25512M2018L/AS9C25256M2018L
T - 144
Top view
VDDQA
DQ4B
DQ4A
DQ3B
DQ3A
VSS
VDDQB
DQ2B
DQ2A
DQ1B
DQ1A
DQ0B
DQ0A
VSS
VDDQA
NC
74
73
VDDQA
OPTB
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
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®
Signal description
Signal
Port A
CLKA
Port B
CLKB
I/O Properties
Description
Notes
Clock. Each port has an independent Clock input that can be of different frequencies. All
I
CLOCK
1
6
inputs except OE and ZZx are synchronous to the corresponding port’s clock and must meet
x
setup and hold time about the rising edge of the clock.
A0A - A18A
DQ0A - DQ17A DQ0B - DQ17B I/O
A0B - A18B
I
SYNC
SYNC
External Address. Sampled on the rising edge of corresponding port clock
Bidirectional data pins
Chip enable inputs. Active low and high, respectively. Sampled on the rising edge of
corresponding port clock.
CE0A, CE1A
R/WA
CE0B, CE1B
R/WB
I
I
I
SYNC
SYNC
SYNC
Read/Write enable. Drive this pin LOW to write to, or HIGH to Read from the memory array.
Byte Enable Inputs. Active low. Asserting these signals enables Read and Write operations to
the corresponding bytes of the memory array. (Refer Byte Control Truth Table)
Address Strobe Enable.Active low. Loads external address onto the counter. (Refer Counter
Control Truth Table)
BE0A - BE1A BE0B - BE1B
ADSA
INCA
RPTA
OEA
ADSB
INCB
RPTB
OEB
I
I
I
I
I
SYNC
SYNC
Address Counter Increment. Active low. Increments the counter value. (Refer Counter Control
Truth Table)
Address Counter Repeat. Active low. Reloads the counter with the previously loaded external
address.(Refer Counter Control Truth Table)
SYNC
Asynchronous output enable. I/O pins are driven when the OE is low and the chip is in Read
mode. A high on OE tristates the I/O pins.
ASYNC
ASYNC
Snooze Mode Input. Places the device in low power mode. Data is retained. This pin has an
internal pull-down and can be floating.
ZZA
ZZB
Pipeline/Flow-Through Select. When low, enables single register flow-through mode. When
PL/FTA
PL/FTB
I
I
STATIC high, enables double register Pipeline mode. This pin has an internal pull-up and can be left
floating to operate in pipeline mode.
VDDQx Option. OPTx selects the operating voltage levels for the I/Os, addresses, clock, and
STATIC controls on that port. This pin has an internal pull-up and can be left floating to operate in 3.3V 1,2,3
OPTA
INTA
OPTB
INTB
mode.
Interrupt Flag. Used for message passing between two ports. (Refer Interrupt Logic Truth
Table)
O
O
SYNC
SYNC
5
5
Collision Alert Flag. Used to indicate collision during simultaneous memory access to the
same location by both the ports (Refer Collision Detection Truth Table)
COLA
COLB
VDDQA
VDDQB
I
I
I
POWER Power to I/O bus. Can be 3.3V or 2.5V depending on OPTx input.
POWER Power Inputs (To be connected to 2.5V Power supply)
GROUND Ground Inputs (To be connected to Ground supply)
1,2,3
2
VDD
VSS
CLOCK
TCK
TDI
I
I
JTAG Test Clock Input. All JTAG signals except TRST are synchronous to this clock.
(JTAG)
4,5
4,5
5
SYNC
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
(JTAG)
SYNC
(JTAG)
SYNC
(JTAG)
ASYNC
(JTAG)
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
tristated except when the captured data is shifted out of the JTAG TAP.
JTAG Test Mode Select Input. It controls the JTAG TAP state machine. State machine
transitions occur on the rising edge of TCK.
TDO
TMS
TRST
O
I
4,5
4,5
I
JTAG Test Reset Input. Asynchronous input used to initialize TAP controller.
Notes:
1. Subscript 'x' represents 'A' for Port A and 'B' for Port B.
2. OPT ,VDDQ and VDD must be set to appropriate operating levels before applying inputs on the I/Os and controls for that port.
x
x
3. OPT = VDD (2.5V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 3.3V level and VDDQ must be supplied at 3.3V.
x
x
OPT = VSS (0V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 2.5V level and VDDQ must be supplied at 2.5V.
x
x
Each port can independently operate on either of the VDDQ levels.
4. If unused JTAG inputs may be left unconnected.
5. JTAG, Collision Detection & Interrupt features are not supported in TQFP package.
6. Address A18 is a NC for AS9C25256M2018L.
9/24/04, v.1.2
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®
Byte control truth table[1,2,3,4,5]
BE1
H
BE0
H
CLK
L to H
L to H
L to H
Mode
All Bytes Deselected - NOP
H
L
Read or Write Byte 0
Read or Write Byte 1
L
H
Notes:
1. L = low, H = high
2. CE0 = L, CE1 = H (Chip in Select mode)
3. R/W = H for a Read operation, R/W = L for a Write operation
4. Byte 1 - DQ[17:9], Byte 0 - DQ[8:0]
5. More than one byte enable may be simultaneously asserted
[1,4]
Read/write control truth table
[2]
[3]
[3,7]
CE
R/W
X
BE
CLK
L to H
L to H
L to H
L to H
Operation
DQn[0:8]
n
[5,9]
H
L
L
L
X
H
L
L
Chip Deselect
Byte Deselect
Byte Write
Hi-Z
Hi-Z
Din
[5,9]
X
[6]
L
[5,8]
H
Byte Read
Qout
Notes:
1. L = low, H = high, X = don't care
2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H)
3. BE refers to any one of the 2 byte controls [n = 1 or 0] and DQ refers to the corresponding Byte
n
n
4. Snooze de-asserted (ZZ=L)
5. True in flow-through mode. For Pipeline mode there will be a 1 cycle latency [refer timing diagrams]
6. For a write command issued before the completion of a read command, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.
7. All DQs are tristated on power-up
8. OE should be asserted (OE = L) (Refer Read timing waveform)
9. In pipeline mode the DQs are HighZ-ed in the same cycle if R/W=L
[1,2,5,6]
Counter control truth table
Previous
Address
Accessed
Mirror
External
Address
Register
Address
Accessed
[3]
[3]
[3]
[4]
CLK
L to H
L to H
L to H
L to H
ADS
L
INC
X
RPT
H
Content
Operation
[4]
An
X
X
An
An
X
An
An
An + 1
An
Load
H
L
H
Am
Increment
Hold
H
H
H
X
Am
X
X
L
X
Am
Am
Repeat
Notes:
1. L = low, H = high, X = don't care
2. Cycle can be Read, Write or Deselect (Controlled by appropriate setting of R/W, CE0, CE1 and BE )
n
3. ADS, INC, RPT are independent of all other memory controls including R/W, CE0,CE1 and BE (i.e Counter works independent of R/W, CE0,CE1 and BE )
n
n
4. The 'Mirror register' used for the Repeat operation is loaded with External address during every valid ADS access. “Am” refers to the mirror register content.
5. Clock to the counter is disabled during Snooze mode (True for both ports).
6. The counter and the mirror registers are not initialized on Power-up (refer Counter description).
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®
Package Thermal Resistance
Description
Conditions
Symbol
Typical
Units
BGA
fpBGA
TQFP
θ
TBD
TBD
TBD
°C/W
°C/W
°C/W
JA
Thermal Resistance (junction to
ambient)
θ
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
[1]
JA
θ
JA
Thermal Resistance (junction to
θ
TBD
°C/W
[1]
JC
top of case)
Notes:
1. This parameter is sampled.
[1]
[2]
Capacitance (T = +25 °C, F = 1.0 Mhz)
A
BGA
(Max)
f p B G A
(Max)
TQFP
(Max)
[3]
Parameter
Symbol
Signals
Test Condition
= L to H or H to L
IN
Unit
Address and
Control pins
Input Capacitance
C
V
TBD
TBD
TBD
pF
IN
Output Capacitance
I/O Capacitance
C
Flag Output pins
I/O pins
V
= L to H or H to L
= L to H or H to L
TBD
TBD
TBD
TBD
TBD
TBD
pF
pF
OUT
OUT
C
V
I/O
I/O
Notes:
1. Sampled, not 100% tested
2. T stands for 'Ambient temperature'.
A
3. L = 0V; H = 3V
[1]
Absolute maximum ratings
Rating
Parameter
Symbol
VDD
Min
-0.5
-0.3
-0.3
-
Max
3.6
Unit
Core supply voltage relative to VSS
I/O supply voltage relative to VSS
Input and I/O voltage relative to VSS
Power Dissipation
V
V
VDDQ
3.9
V
VDDQ + 0.3
TBD
V
IN
P
W
mA
°C
°C
°C
D
Short circuit output current
Storage Temperature
I
-
TBD
OUT
T
-65
-55
-
150
STG
Storage Temperature under Bias
Junction Temperature
T
125
BIAS
T
TBD
JN
Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating for extended
periods may affect reliability.
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AS9C25256M2018L
®
Recommended operating Temperature
Grade
Commercial
Industrial
Ambient Temperature (T )
A
0°C to 70°C
-40°C to 85°C
Recommended operating conditions
[1]
[2]
VDDQ = 2.5V
VDDQ = 3.3V
Typ
Parameter
Core Supply Voltage
I/O supply Voltage
Ground
Symbol
VDD
Min
2.4
2.4
0
Typ
2.5
2.5
0
Max
2.6
2.6
0
Min
2.4
3.15
0
Max
2.6
3.45
0
Unit
V
2.5
3.3
0
VDDQ
VSS
V
V
Notes:
1. OPT pin for a given port must be set to VSS(0V) to operate at VDDQ = 2.5V levels on the I/Os, addresses, clock and controls of that port.
2. OPT pin for a given port must be set to VDD(2.5V) to operate at VDDQ = 3.3V levels on the I/Os, addresses, clock and controls of that port.
DC Electrical Characteristics (VDD = 2.5 V ± 100 mV)
VDDQ = 2.5V
VDDQ = 3.3V
Min
Parameter
Symbol
Test Conditions
Min
Max
Test Conditions
VDDQ = Max;
Max
Units
VDDQ = Max;
Input Leakage
Current
|ILI
|ILI
|
|
-
2
-
-
-
2
2
2
µA
µA
µA
0V < VIN < VDDQ
VDD = Max;
0V < VIN < VDDQ
VDD = Max;
PL/FT and ZZ Input
Leakage Current
-
-
2
2
0V < VIN < VDD
OE>=VIH;
0V < VIN < VDD
OE>=VIH;
Output Leakage
Current[1]
|ILO
|
0V < VOUT < VDDQ
0V < VOUT < VDDQ
Input high (logic 1)
voltage
(Address, Control,
Clock & Data Inputs)
VIH
VIH
VIL
-
-
1.7
VDDQ + 0.1V
-
-
2
VDDQ + 0.15V
VDD + 0.1V
0.8
V
V
V
Input high voltage
(ZZ,OPT,PL/FT)
VDD - 0.2V VDD + 0.1V
VDD - 0.2V
-0.3
Input low (logic 0)
voltage (Address,
Control, Clock &
Data Inputs)
-
-
-0.3
0.7
-
-
Input low voltage
(ZZ,OPT,PL/FT)
VIL
-0.3
-
0.2
0.4
-0.3
-
0.2
0.4
V
V
IOL = +2mA;
VDDQ = Min
IOH = -2mA;
VDDQ = Min
IOL = +4mA;
VDDQ = Min
IOH = -4mA;
VDDQ = Min
Output low voltage
VOL
Output high voltage
Notes:
VOH
2.0
-
2.4
-
V
1. Outputs disabled (High-Z condition).
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AS9C25512M2018L
AS9C25256M2018L
®
[4]
I
operating conditions and maximum limits (VDD = 2.5 V ± 100 mV)
DD
Parameter
Symbol
Test Conditions
-250
-200
-166
-133
Units
Typ Max Typ Max Typ Max Typ Max
Operating current
(Both ports active)
TBD TBD TBD 350 TBD 300 TBD 260
mA
Both ports enabled (CEA = CEB = L[3]),
Pipeline mode --
(PL/FT > VIH
)
ICC
Outputs disabled (IOUT = 0mA), ZZA = ZZB < VIL,
Operating current
(Both ports active)
[1]
f=fMax
TBD TBD TBD TBD TBD TBD TBD TBD
mA
Flow-through mode
(PL/FT < VIL)
Both ports disabled (CEA = CEB = H),
Standby current
(Both ports)
TBD TBD TBD 105 TBD
90
TBD
80
ISB1 ZZA = ZZB < VIL,
mA
mA
mA
[1]
f=fMax
One port enabled (CEA = L and CEB = H)[5]
,
Standby current
(One port)
TBD TBD TBD 265 TBD 225 TBD 190
ISB2 Active port's outputs disabled, ZZA = ZZB < VIL,
[1]
f=fMax
Both ports disabled (CEA = CEB = H),
Full standby current
(Both ports)
20
25
20
25
20
25
20
25
ISB3 ZZA = ZZB < VIL,
f=0[2]
One port in Snooze (ZZA > VIH, ZZB < VIL, and
CEB = L)[5]
,
Full standby current
(One port)
TBD TBD TBD 265 TBD 225 TBD 190
ISB4
mA
mA
Active port's outputs disabled,
[1]
f=fMax
Both ports in Snooze (ZZA = ZZB > VIH),
Snooze mode
current
15
18
15
18
15
18
15
18
IZZ
[1]
f=fMax
Notes:
1. f=fMax implies address and controls (except OE) are cycling at maximum clock frequency using AC test conditions (Refer AC test conditions).
2. f = 0 implies address and controls are static. Corresponding current numbers indicated are true for both CMOS (V > VDDQ - 0.2V or V < 0.2V)
IN
IN
and TTL (V > V or V < V ) level inputs.
IN
IH
IN
IL
3. CE and CE are internal signals (CE = L implies CE0 < V and CE1 > V , CE = H implies CE0 > V or CE1 < V ).
A
B
x
x
IL
x
IH
x
x
IH
x
IL
4. Subscript 'x' represents 'A' for Port A and 'B' for Port B.
5. “A” and “B” are interchangeable.
9/24/04, v.1.2
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AS9C25512M2018L
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®
[1,2,5,6]
AC timing characteristics
(VDD = 2.5 ± 100mV)
Parameter
Symbol
-250
-200
-166
-133
Unit Notes
Min. Max. Min. Max. Min. Max. Min. Max.
Clock
tCYCP
tCHP
tCLP
4
5
2
6
7.5
3
ns
ns
ns
ns
ns
ns
3
3
3
3
3
3
Cycle Time (Pipeline)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.7
1.7
6.5
1.7
1.7
2.4
2.4
10
Clock High Pulse Width (Pipeline)
Clock Low Pulse Width (Pipeline)
Cycle Time (Flow-Through)
Clock High Pulse Width (Flow-Through)
Clock Low Pulse Width (Flow-Through)
Output
2
3
tCYCF
tCHF
tCLF
7.5
2
12
3
2.4
2.4
2
3
tCDP
tOHP
2.8
-
-
2.8
6.5
-
3.4
-
-
3.4
7.5
-
3.6
-
-
3.6
10
-
4.2
-
-
4.2
12
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
Clock access time (Pipeline)
Output Data Hold from Clock High (Pipeline)
Clock High to Output Low-Z (Pipeline)
Clock High to Output High-Z (Pipeline)
Clock access time (Flow-Through)
Output Data Hold from Clock High (Flow-Through)
Clock High to Output Low-Z (Flow-Through)
Clock High to Output High-Z (Flow-Through)
Output Enable to Data Valid
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Setup
-
1
1
1
-
1
1
1
-
-
1
1
1
-
1
1
1
-
-
1
1
1
-
1
1
1
-
-
1
1
1
-
1
1
1
-
tLZCP
tHZCP
tCDF
3,8
3,8
3
tOHF
tLZCF
tHZCF
tOE
3,8
3,8
4
-
-
-
-
2.8
2.8
-
3.4
3.4
-
3.6
3.6
-
4.2
4.2
-
tLZOE
tHZOE
1
1
1
1
4
1
2.8
1
3.4
1
3.6
1
4.2
4
tAS
tCES
tBS
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup to Clock High
Chip Enable Setup to Clock High
Byte Enable Setup to Clock High
R/W Setup to Clock High
Input Data Setup to Clock High
ADS Setup to Clock High
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tWS
tDS
tADSS
tINCS
tRPTS
-
-
-
INC Setup to Clock High
RPT Setup to Clock High
Hold
tAH
tCEH
tBH
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
Address Hold from Clock High
Chip Enable Hold from Clock High
Byte Enable Hold from Clock High
R/W Hold from Clock High
Input Data Hold from Clock High
ADS Hold from Clock High
INC Hold from Clock High
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tWH
tDH
tADSH
tINCH
tRPTH
RPT Hold from Clock High
Flag
tSINT
tRINT
tSCOL
tRCOL
6
6
6
7
ns
ns
ns
ns
Interrupt Flag Set Time
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
6
6
7
2.8
2.8
3.4
3.4
3.6
3.6
4.2
4.2
Port-to-Port Delay
tCCO
3.0
3.5
4
5
ns
7
Clock-to-Clock Delay
-
-
-
-
Notes:
1. All timings are same for both ports.
2. These values are valid for either level of VDDQ (2.5V/3.3V)
3. A particular port will operate in Pipeline output mode if PL/FT = VDD and in flow-through output mode if PL/FT = 0V. Each port can independently operate in any of these
modes.
4. Output Enable (OE) is an asynchronous input.
5. PL/FT and OPT should be treated as DC signals and should reach steady state before normal operation.
6. Refer AC Test Conditions to view the test conditions used for these measurements.
7. This parameter has to be taken care to avoid collision during simultaneous memory access of the same location.
8. To avoid bus contention, at a given voltage and temperature t
is more than t
(True in both Pipeline and flow-through output mode).
LZC
HZC
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[7]
Timing waveform of read cycle
Don’t care
Undefined
[2]
tCYC
tCL
tCH
CLK
tCES
tCEH
CE[3]
tBS
tBH
BEn[4]
R/W
tWH
tWS
tAS
tAH
[5]
ADDRESS
A6
A11
A12
A13
A2
A3
A4
A5
A7
A10
A8
A9
A1
tLZOE
OE[6]
[Pipeline Mode]
tOHP
tHZCP
tHZOE
tOE
tLZCP
DATA OUT[1]
[Pipeline Mode]
Q1
Q10
Q2
Q6
Q8
tLZOE
tCDP
tLZOE
OE[6]
[Flow-through Mode]
tOHF
tHZCF
tHZOE
tOE
tLZCF
DATA OUT[1]
Q12
Q1
Q10
Q2
Q8
Q6
[Flow-through Mode]
tLZOE
tCDF
Read[8] Dsel
(A4)
Read
(A10)
Read
(A12)
Read
(A1)
Read
(A2)
Read
(A6)
Read
(A7)
Read
(A8)
Dsel
Dsel
Dsel
Notes:
1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters t
, t and t are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics).
CYC CH
CL
3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1
4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte.
5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H).
6. OE is an asynchronous input.
7. All timings are similar for both ports.
8. Read with Byte disabled. Data is not read out.Bus in High-Z condition.
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[7]
Timing wave form read/write cycle
[2]
Don’t care
tCYC
tCL
Undefined
tCH
CLK
tCES
tCEH
CE[3]
tBS
tBH
BEn[4]
R/W
tWH
tWS
tAS
tAH
[5]
ADDRESS
A5
A10
A11
A12
A2
A3
A3
D3
A4
A6
D6
A9
A7
A8
D8
A1
OE[6]
[Pipeline Mode]
tDS
tDH
[1]
DATA IN
[Pipeline Mode]
tCDP
tHZCP
tHZOE
[1]
DATA OUT
Q9
Q1
[Pipeline Mode]
tLZCP
OE[6]
[Flow-through Mode]
[1]
DATA IN
D3
D6
D11
[Flow-through Mode]
tHZCF
tOHF
tCDF
tHZOE
tDS
tDH
[1]
DATA OUT
Q9
Q4
Q7
Q2
Q1
[Flow-through Mode]
tLZCF
Write[8] Write
(A3)
Read
(A4)
Read
(A5)
Write
(A6)
Read
(A7)
Write[9] Read
(A9)
(A8)
Write[9]
(A11)
Read
(A1)
Read
(A2)
Dsel
Notes:
1. Both Flow-through and Pipeline Inputs/Outputs indicated.A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters t
,t and t are different in Flow-through and Pipeline modes of operation.(Refer AC Timing characteristics)
CYC CH
CL
3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1
4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte.
5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H).
6. OE is an asynchronous input.
7. All timings are similar for both ports.
8. Invalid write. Memory Content of the selected location may get corrupted and should be re-written before future readback.
9. Write (A11) is invalid in Pipeline mode and Write (A8) is invalid in Flow-through mode. Memory Content of the selected location may get corrupted and should be re-written
before future readback.
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®
[6]
Timing waveform of address counter
[2]
tCYC
tCL
Don’t care
Undefined
tCH
CLK
CE[3]
tCES
tCEH
[4]
R/W
tWH
tWS
tAS
tAH
ADDRESS
A2
A1
INTERNAL
ADDRESS
A2+1
A1+1
A1+2
A2
A2
A1+2
A1
A1+2
A2+1
A1+2
A1+1
A1
tADSS
tADSH
ADS
INC
tINCS
tINCH
tRPTS
tRPTH
RPT
tDS
tDH
DATA IN
D1
D1+2
D1+2
D1+1
tCDP
tOHP
tHZCP
[5]
DATA OUT[1]
[Pipeline Mode]
Q1
Q1+2
Q1+1
tLZCP
tHZCF
tOHF
tCDF
[5]
DATA OUT[1]
[Flow-through Mode]
Q1+1
Q1+2
Q1
tLZCF
Write
Load
(A1)
Write
Incr
Write
Incr
Write
Hold
Dsel
Rept
Read
Rept
Read
Incr
Read
Hold
Dsel
Incr
Read
Incr
Dsel
Dsel
Hold
Load
(A2)
Notes:
1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters t
,t and t are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics).
CYC CH
CL
3. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1.
4. These cycles indicate that Counter works independent of all memory controls including R/W,CE and BEn.
5. If a Hold operation is performed for a Read access, the Data-out is held valid for the subsequent clock cycle also.
6. All timings are similar for both ports.
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Mailbox Interrupts
The AS9C25512M2018L/AS9C25256M2018L has an Inbuilt Mailbox Logic that can be used for communication between the two ports.
One memory location is assigned as mail box (message center) for each port. The location 7FFFE (HEX) is assigned as the message center
for Port A and 7FFFF (HEX) for Port B (3FFFE and 3FFFF for AS9C25256M2018L). The port A interrupt flag (INTA) is asserted when the
port B writes to memory location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). The port A clears the interrupt flag by reading the
address location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). Likewise, the port B interrupt flag (INTB) is asserted when the port A
writes to memory location 7FFFF (HEX) (3FFFF for AS9C25256M2018L) and to clear the interrupt flag (INTB), the port B must read the
memory location 7FFFF (3FFFF for AS9C25256M2018L).(Refer Interrupt Logic Truth Table).
The interrupt flag is asserted in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-
through mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without de-asserting the
interrupt and each port can write to its own mailbox without asserting the interrupt. If an application does not require message passing, INT
pins can be ignored.
[1,4,5]
Interrupt logic truth table
[2]
[3,6]
[2]
[3,6]
Function
CLKA R/WA CEA
A18A-A0A
CLKB R/WB CEB
A18B-A0B
INTA INTB
L to H
L to H
L to H
L to H
Notes:
L
X
X
H
L
X
X
L
7FFFF
L to H
L to H
L to H
L to H
X
H
L
X
L
L
X
X
X
X
L
L
H
X
X
Assert Port B Interrupt Flag
De-assert Port B Interrupt Flag
Assert Port A Interrupt Flag
De-assert Port A Interrupt Flag
X
X
7FFFF
7FFFE
X
7FFFE
X
H
1. L = low, H = high, X = don't care
2. CE is an internal signal ('x' = 'A' or 'B'). CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H)
x
x
x
x
x
x
x
3. Address specified here is the internal address (refer Counter control truth table).
4. Both Interrupt Flags are De-asserted on power-up.
5. Interrupt feature is not supported in TQFP package.
6. Address A18 is a NC for AS9C25256M2018L, hence Interrupt addresses are 3FFFF and 3FFFE
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[2]
Interrupt timing wave form
[1]
t
Don’t care
CYC
CLKA
[1]
CL
[1]
CH
t
t
t
WS
t
WH
[2]
R/WA
t
AS
t
AH
[4]
7FFFF
[5]
Aa
[3]
ADDRESSA
Aa
Aa
Aa
7FFFF
Aa
7FFFE
t
t
SINT
RINT
INTA
[1]
CYC
t
CLKB
[1]
t
CL
[1]
CH
t
t
WS
t
WH
[2]
R/WB
t
AS
t
AH
[5]
Ab
[4]
7FFFE
[3]
ADDRESSB
Ab
7FFFF
Ab
Ab
Ab
7FFFE
t
t
SINT
RINT
INTB
Notes:
1. Parameters t
,t and t are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).
CYC CH
CL
2. Chip Selected (CE0 = L and CE1 =H). True for both ports.
3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.
4. 7FFFF (3FFFF for AS9C25256M2018L) is the Mailbox for port B and 7FFFE (3FFFE for AS9C25256M2018L) is the Mailbox for port A.
5. “Aa” and “Ab” refer to any other valid address other than 7FFFF or 7FFFE (3FFFF or 3FFFE for AS9C25256M2018L).
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Collision detection
Three different cases of collisions can be listed depending on the type of access from two ports:
Simultaneous Read: A true dual-ported memory cell allows data to be read simultaneously from both ports of the device. Hence no data is
corrupted, lost, or incorrectly output, and none of the collision alert flags is asserted.
Simultaneous Write: When both ports are writing simultaneously to the same location, both write operations would fail. Therefore, the
collision flag is asserted on both ports.
Simultaneous Read and Write: When one port is writing and the other port is reading from the same location in the memory, the data
written will be valid. However, the read operation would fail and hence the reading port's collision flag is asserted.
The alert flag (COLx) is asserted on the 3rd (for both pipe-lined and flow-through output mode) rising clock edge of the affected port
following the collision, and remains low for one cycle. On continuous collisions (one or both ports writing during each access), the collision
alert flag will be asserted and de-asserted every alternate cycle.
[1,2,4,5]
Collision detection truth table
Port address[3]
COLA
COLB
Function
CLKA
R/WA
CLKB
R/WB
Both ports reading. Not a valid collision. No
collision flag asserted on either port.
L to H
H
L to H
H
MATCH
H
H
Port A reading, Port B writing. Valid collision.
Collision flag asserted on port A.
L to H
L to H
L to H
L to H
H
L
L
L
L to H
L to H
L to H
L to H
L
H
L
MATCH
MATCH
L
H
L
H
L
L
H
Port B reading, Port A writing. Valid collision.
Collision flag asserted on port B.
Both ports writing. Valid collision. Collision
flag asserted on both ports.
MATCH
No match. No collision flag asserted on either
port.
H
NO MATCH
H
Notes:
1. L = low, H = high, X = don't care
2. Chip Selected (CE0 = L and CE1 =H). True for both ports. Collision flag is not affected if any one or both ports are deselected.
3. “MATCH” indicates that internal addresses of both the ports are the same (refer Counter control truth table).
4. Both Collision Flags are De-asserted on power-up.
5. Collision detection feature is not supported in TQFP package.
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[2]
Collision timing waveform
Don’t care
[1]
tCYC
CLKA
[1]
[1]
tCH
[5]
tCL
tWS
tWH
tCCO
R/WA
tAS
tAH
[4]
Am
[3]
ADDRESSA
Am
Am
Aa
Aa
Aa
Aa
Aa
Am
Am
Am
Am
tSCOL tRCOL
COLA
[1]
tCYC
CLKB
R/WB
[1]
[1]
tCL
tCH
tWS
tWH
tAS
tAH
[4]
[3]
ADDRESSB
Am
Am
Ab
Ab
Am
Ab
Ab
Ab
Am
Am
Am
Am
tSCOL
tRCOL
COLB
Notes:
1. Parameters t
,t and t are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).
CL
CYC CH
2. Chip Selected (CE0 = L and CE1 =H). True for both ports.
3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.
4. “Am” refers to matched address. “Aa” and “Ab” refer to any other valid address.
5. During address collision the data validity is guaranteed only if t
is greater than the minimum specified (Refer AC timing characteristics).
CCO
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Depth and Width expansion
AS9C25512M2018L/AS9C25256M2018L has two chipselects (one active high and other active low) for simple depth expansion. This
permits easy upgrade from 512/256K depth to 1M/512K depth without extra logic. Two such parts can also be combined to obtain an
expanded width of 36 bits or wider.
DQ<0:35>
Data
Address
[2]
A<0:19>
Microprocessor
Clock
CE0
CE1
CE0
CE1
Clock
CLK
R/W
BE<0:1>
OE
CLK
R/W
BE<0:1>
OE
512/256Kx18
DPSRAM
512/256Kx18
DPSRAM
Controller
ADS
ADS
INC
RPT
INC
RPT
BANK 1
BANK 0
Notes:
1. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L
2. A<0:19> for AS9C25512M2018L, A<0:18> for AS9C25256M2018L
3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L
[4,5,6]
Timing waveform of multi device read
[1]
tCYC
tCL
Don’t care
Undefined
tCH
CLK
tWS
tWH
R/W
tAS
tAH
A[0:18][2]
A1
A2
A5
A4
A6
A8
A3
Q1
A7
A[19][3]
tCDP
tOHP
tHZCP
DATA OUT [0:35]
Q2
Q4
(BANK 0)
[Pipeline Mode]
tOHP
tHZCP
tCDP
tLZCP
DATA OUT [0:35]
Q6
Q5
Q3
(BANK 1)
[Pipeline Mode]
tOHF
tHZCF
tCDF
tLZCP
DATA OUT [0:35]
(BANK 0)
Q1
Q2
Q4
[Flow-through Mode]
tHZCF
tCDF
tOHF
tLZCF
DATA OUT [0:35]
(BANK 1)
Q3
Q5
Q6
[Flow-through Mode]
tLZCF
Read
(Bank1)
Read
(Bank0)
Read
(Bank1)
Read
(Bank1)
Read
(Bank0)
Read
(Bank0)
Read
(Bank0)
Notes:
1. Parameters t
, t and t are different in Flow-through and Pipeline mode of operation (Refer AC Timing characteristics).
CYC CH
CL
2. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L
3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L
4. Refer to the above block diagram for the assumed setup.
5. One Bank is assumed to have two AS9C25512M2018L/AS9C25256M2018Ls combined to have an expanded width of 36 bits. Two such Banks are used for depth expansion.
6. All BEn's = L, Counter set in “Load” mode (ADS = L, INC = X, RPT = H), OE =L.
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Snooze mode
Snooze mode is a low-current, power-down mode in which the corresponding port is deselected and its current is reduced to a
very low value. Both ports are equipped with independent SNOOZE inputs (ZZ). During Snooze mode, all inputs of the port
except ZZ are internally disabled and all its Outputs go to High-Z.
ZZ is an asynchronous, active HIGH input that causes the selected port to enter Snooze mode. If both ports go into Snooze mode,
the device is deselected and current is reduced to IZZ. When ZZA and ZZB become a logic HIGH, IZZ is guaranteed after the
setup time tSCZZ is met.
Any READ or WRITE operation pending when the port enters Snooze mode is not guaranteed to complete. Therefore, Snooze
mode must not be initiated until valid pending operations are completed. Similarly during the time tRCZZ, when the port is
transitioning out of snooze mode, only DESELECT cycles should be given.
Snooze mode electrical characteristics
Description
Conditions
Symbol
Min
Max
Units
mA
SNOOZE MODE Current
ZZ = ZZ >= V
I
ZZ
15
-
18
2
-
A
B
IH
ZZ active to input ignored
t
cycle
cycle
cycle
cycle
SCZZ
RCZZ
ZZ inactive to input sampled
ZZ active to enter Snooze Current
ZZ inactive to exit Snooze Current
t
2
-
t
2
-
SIZZ
RIZZ
t
0
[1,3]
Snooze mode timing waveform
Don’t care
Undefined
tCYC
CLK
tCES
tCH
tCL
tCEH
CE[2,4]
ZZ
tSIZZ
tRIZZ
ISupply
IZZ
tRCZZ
tSCZZ
ZZ recovery cycles
ZZ setup cycles
INPUTS
Valid
Valid
tLZC
(Except ZZ)
tHZC
OUTPUTS[5]
(Qout)
High-Z
Notes:
1. During Snooze mode, all dynamic inputs are disabled (except JTAG inputs). During JTAG operations, ZZ must be held Low in order to capture the parallel inputs of the bound-
x
ary scan register. All static inputs (i.e. PL/FT ,OPT ) and ZZ themselves are not affected during snooze mode.
x
x
x
2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
3. All timings are same for Port A and Port B.
4. Minimum of two deselect cycles should be given before asserting snooze and minimum of two deselect cycles should be given after de-asserting snooze to guarantee data
integrity.
5. Select cycles indicated before and after Snooze are Read cycles. They can also be Write cycles.
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AC test conditions
Input Pulse Level (Address and Controls)
GND to 3.0V/GND to 2.4V
GND to 3.0V/GND to 2.4V
2V/ns
Input Pulse Levels (I/Os)
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference levels
1.5V/1.25V
1.5V/1.25V
Output Load (for t
, t
, t
, t
)
Fig. C
LZC HZC LZOE HZOE
Output Load (for all other measurements)
Fig. B
Thevenin equivalent:
+3.3/2.5 V;
+3.0/2.4 V
90%
10%
Figure A: Input Waveform
90%
Z0 = 50Ω
50 Ω
319Ω / 1667
Ω
10%
D
OUT
GND
VL = 1.5/1.25 V
10 pF*
5 pF*
353Ω / 1538
Ω
Figure B: Output Load (A)
GND
Figure C: Output Load (B)
* Including scope and jig capacitance
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IEEE 1149.1 Serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan Test Access Port (TAP). All JTAG pins operate using JEDEC standard 2.5V I/O logic levels.
In order to operate the device without using the JTAG feature, all JTAG pins may be left unconnected. On power-up, the device will start in
a reset state which will not interfere with normal device operation.
TAP Controller block diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1 0
3
Instruction Register
TDI
TDO
3130 29 .
. .
2 1 0
Identification Register
[1]
.
. . . .
2
1 0
x
1
Boundary Scan Register
TCK
TMS
TAP Controller
Note:
1. x = 111
JTAG timing waveform
tJCYC
Don’t care
Undefined
tJCH
tJCL
TEST CLK
TCK
tJIH
tJIS
TMS/TDI
tJCD
TDO
tJOH
tJRS
tJRR
TRST
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[2]
TAP AC electrical characteristics
Description
Symbol
Min
Max
Units
Clock
Clock cycle time
Clock frequency
Clock high time
Clock low time
Output Times
TCK low to TDO unknown
TCK low to TDO valid
Setup Times
t
100
-
-
10
-
ns
MHz
ns
JCYC
f
JTAG
t
40
40
JCH
t
-
ns
JCL
t
0
-
-
ns
ns
JOH
t
20
JCD
TMS/TDI setup
Capture setup
t
10
10
-
-
ns
ns
JIS
[1]
t
JCS
Hold Times
TMS/TDI hold
Capture hold
t
10
10
-
-
ns
ns
JIH
[1]
t
JCH
Reset Times
JTAG Reset
t
50
50
-
-
ns
ns
JRS
JTAG Reset Recovery
Notes:
t
JRR
1. t
and t
refer to the setup and hold time requirements of latching data from the boundary scan register.
JCS
JCH
2. Test conditions are specified using the load in the figure TAP AC output load equivalent.
TAP AC test conditions & output load equivalent
Input pulse levels
Vss to 2.5V
1V/ns
1.25V
50Ω
20pF
Input rise and fall times
Input timing reference levels
Output reference levels
1.25V
TDO
1.25V
ZO=50Ω
Test load termination supply voltage
1.25V
TAP DC electrical characteristics and operating conditions (VDD=2.5V ± 100 mV)
Description
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current
Output leakage current
Output low voltage
Symbol
Conditions
Min
Max
Units
V
V
1.7 VDD + 0.3
IH
V
-0.3
0
0.7
10
V
IL
|I |
VDD = Max; 0V < V < VDD
µA
µA
V
LI
IN
|I
|
Outputs disabled, 0V < V
< VDDQ (DQ )
0
10
LO
OUT
x
V
I
= 100µA
0.2
0.7
OLC
OLC
Output low voltage
V
I
= 2mA
OLT
V
OLT
OHC
OHT
Output high voltage
Output high voltage
V
V
I
= -100µA
2.1
1.7
V
OHC
I
= -2mA
V
OHT
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Identification register definitions
Instruction field
Value
TBD
TBD
Description
Version Number
ALSC part number
Revision number (31:28)
Device depth (27:12)
Manufacturer Identity Code
(ALSC)
JEDEC ID code (11:1)
Indicator Bit (0)
00001010010
1
ID Register presence indicator
Scan register sizes
Register name
Bit size
Instruction Register (IR)
Bypass Register (BYR)
4
1
Identification Register (IDR)
Boundary Scan Register (BSR)
32
112
Instruction codes
Instruction
Code
Description
Selected Reg
EXTEST
0000
Forces contents of the BSR onto the device outputs.
BSR
Samples the I/O ring contents. Preloads test data into the
BSR.
SAMPLE/PRELOAD
IDCODE
0001
BSR
IDR
Loads the IDR with the vendor ID code and places the
register between TDI and TDO.
0010
CLAMP
0011
0100
Forces contents of the BSR onto the device outputs.
Forces all device 2-state and 3-state outputs to High-Z.
BYR
BYR
BYR
BYR
HIGHZ
RESERVED
BYPASS
0101 - 1110 Reserved states. Do not use.
1111 Places the BYR between TDI and TDO.
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Package Diagram: 256-ball Ball Grid Array (BGA)
All measurements are in
mm.
Min Typ Max
A
B
C
D
E
F
G
H
I
1.00
16.95 17.00 17.05
15.00
16.95 17.00 17.05
15.00
0.36
0.35
0.50
1.60
0.40 0.50 0.60
0.70
J
Top View
Bottom View
A1 corner index
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
oooooooooooooooo
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
+
oooooooooooooooo
A
B
oooooooooooooooo
+
oooooooooooooooo
+
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
C
oooooooooooooooo
+
+ +
+
A
D
E
D
J
0.35 Z
oooooooooooooooo
o
o
I
G
0.20 Z
H
F
/ 0.50±0.10 (256X)
o o
M
M
Ø 0.25 Z X Y
Ø 0.15
Z
Side View
Detail of Solder Ball
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Package Diagram: 208-ball fine pitch Ball Grid Array (fpBGA)
All measurements are in
mm.
Min Typ Max
A
B
C
D
E
F
G
H
I
0.80
14.95 15.00 15.05
12.80
14.95 15.00 15.05
12.80
0.26
0.25
0.40
1.40
0.40 0.45 0.50
0.70
J
Bottom View
Top View
A1 corner index
17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
ooooooooooooooooo
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
+
ooooooooooooooooo
ooooooooooooooooo
A
B
+
ooooooooooooooooo
+
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
C
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
+
+ +
+
A
D
E
J
D
0.20 Z
ooooooooooooooooo
o
o
I
G
0.15 Z
H
F
/ 0.45±0.05 (208X)
o o
M
M
Ø 0.15 Z X Y
Ø 0.08
Z
Detail of Solder Ball
Side View
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Package Diagram: 144-pin Thin Quad Flat Pack (TQFP)
TQFP
Min
0.05
1.35
0.17
0.09
Typ
Max
0.15
1.45
0.27
0.20
A1
A2
b
1.40
0.20
c
D
20.00 nominal
20.00 nominal
0.50 nominal
22.00 nominal
22.00 nominal
Hd
D
E
e
Hd
He
L
b
e
0.45
0.60
1.00 nominal
3.5°
0.75
L1
α
0°
7°
Dimensions in millimeters
He
E
c
α
L1
L
A1 A2
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Ordering Information
Package & Width
512K X 18
-250
-200
-166
-133
AS9C25512M2018L - 250BC AS9C25512M2018L - 200BC AS9C25512M2018L -166BC AS9C25512M2018L - 133BC
AS9C25512M2018L - 250BI AS9C25512M2018L - 200BI AS9C25512M2018L - 166BI AS9C25512M2018L - 133BI
AS9C25512M2018L - 250FC AS9C25512M2018L - 200FC AS9C25512M2018L - 166FC AS9C25512M2018L - 133FC
AS9C25512M2018L - 250FI AS9C25512M2018L - 200FI AS9C25512M2018L - 166FI AS9C25512M2018L - 133FI
AS9C25512M2018L - 250TC AS9C25512M2018L - 200TC AS9C25512M2018L - 166TC AS9C25512M2018L - 133TC
AS9C25512M2018L - 250TI AS9C25512M2018L - 200TI AS9C25512M2018L - 166TI AS9C25512M2018L - 133TI
BGA X 18
fpBGA X 18
TQFP X 18
256K X 18
AS9C25256M2018L - 250BC AS9C25256M2018L - 200BC AS9C25256M2018L -166BC AS9C25256M2018L - 133BC
AS9C25256M2018L - 250BI AS9C25256M2018L - 200BI AS9C25256M2018L - 166BI AS9C25256M2018L - 133BI
AS9C25256M2018L - 250FC AS9C25256M2018L - 200FC AS9C25256M2018L - 166FC AS9C25256M2018L - 133FC
AS9C25256M2018L - 250FI AS9C25256M2018L - 200FI AS9C25256M2018L - 166FI AS9C25256M2018L - 133FI
AS9C25256M2018L - 250TC AS9C25256M2018L - 200TC AS9C25256M2018L - 166TC AS9C25256M2018L - 133TC
BGA X 18
fpBGA X 18
TQFP X 18
AS9C25256M2018L - 250TI
AS9C25256M2018L - 200TI
AS9C25256M2018L - 166TI
AS9C25256M2018L - 133TI
Part Numbering Guide
AS
9C
25
512/256
M20
18
L
-XXX
T or B or F
C/I
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor prefix
2. Speciality Memory
3. Operating Voltage: 25 - VDD = 2.5V
4. Device depth: 512 - 512K; 256 - 256K
5. M20 - Multiport - 2port, SSRAM, DCD
6. I/O width - 18
7. I/O interface: L - LVTTL
8. Clock speed (MHz)
9. Package Type: T - TQFP, B - BGA, F - fpBGA
10. Operating Temperature: C - Commercial (00C to 700C); I -Industrial (-400C to 850C)
9/24/04, v.1.2
Alliance Semiconductor
P. 29 of 30
AS9C25512M2018L
AS9C25256M2018L
®
®
Alliance Semiconductor Corporation
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Tel: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: AS9C25512M2018L/
AS9C25256M2018L
Fax: 408 - 855 - 4999
Document Version: v.1.2
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
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