ASM2P3805EG-20-DT [ALSC]
3.3V CMOS Dual 1-To-5 Clock Driver; 3.3V CMOS双1对5时钟驱动器
| 型号： | ASM2P3805EG-20-DT |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V CMOS Dual 1-To-5 Clock Driver |
| 文件： | 总12页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2005
rev 0.2
ASM2P3805X
3.3V CMOS Dual 1-To-5 Clock Driver
Functional Description
Features
Advanced CMOS Technology
The ASM2P3805X is a 3.3V clock driver built using
advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in this document. The ASM2P3805X offers low capacitance
inputs. The ASM2P3805X is designed for high speed clock
distribution where signal quality and skew are critical. The
ASM2P3805X also allows single point-to-point transmission
line driving in applications such as address distribution,
where one signal must be distributed to multiple receivers
with low skew and high signal quality.
Guaranteed low skew < 200pS (max)
Very low propagation delay < 2.5nS (max)
Very low duty cycle distortion < 270pS (max)
Very low CMOS power levels
Operating frequency up to 166MHz
TTL compatible inputs and outputs
Inputs can be driven from 3.3V or 5V components
Two independent output banks with 3-state control
1:5 fanout per bank
ASM2P3805X
Where X =D for 133MHz Operation
X =E for 166MHz Operation
"Heartbeat" monitor output
VCC = 3.3V ± 0.3V
Available in SSOP and QSOP Packages
Pin Diagram
Block Diagram
VCCA
VCCB
OB1
1
2
20
19
OEA
INA
OA1
OA2
5
A
S
M
2
OA1 – OA5
OB2
OB3
GNDB
OB4
OB5
MON
OEB
INB
3
4
18
17
16
15
OA3
GNDA
OA4
5
P
3
5
6
7
INB
OB1 – OB5
MON
8
OA5
0
14
OEB
5
GNDQ
OEA
8
13
12
11
X
9
INA
10
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Pin Description
Pin #
Pin Names
O¯¯EA, O¯¯EB
INA, INB
Description
9,12
10,11
3-State Output Enable Inputs (Active LOW)
Clock Inputs
2,3,4,6,7
OA1-OA5
OB1-OB5
Clock Outputs from Bank A
Clock Outputs from Bank B
19,18,17,15,14
1
20
5
VCCA
VCCB
Power supply for Bank A
Power supply for Bank B
Ground for Bank A
Ground for Bank B
Ground
GNDA
GNDB
GNDQ
MON
16
8
13
Monitor Output
Function Table1
Inputs
Outputs
O¯¯EA, O¯¯EB
INA, INB
OAn, OBn
MON
L
L
L
H
L
L
H
Z
Z
L
H
L
H
H
H
H
Note: 1 H = HIGH; L = LOW; Z = High-Impedance
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter1
Conditions
VIN= 0V
Typ
Max
Unit
pF
Input Capacitance
Output Capacitance
3
4
6
COUT
VOUT = 0V
—
pF
Note: 1 This parameter is measured at characterization but not tested.
3.3V CMOS Dual 1-To-5 Clock Driver
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Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Absolute Maximum Ratings1
Symbol
Description
Max
Unit
V
VCC
VI
Input Power Supply Voltage
-0.5 to +4.6
-0.5 to +5.5
Input Voltage
V
VO
TJ
Output Voltage
-0.5 to VCC+0.5
150
V
Junction Temperature
Storage Temperature
° C
° C
TSTG
-65 to +165
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
TDV
2
KV
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics over Operating Range
Following Conditions Apply Unless Otherwise Specified
Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions1
Min
Typ2 Max
Unit
V
VIH
VIL
Input HIGH Level
2
-
-
5.5
0.8
±1
Input LOW Level
Input HIGH Current
Input LOW Current
-0.5
V
IIH
VCC= Max.
VCC= Max.
VI = 5.5V
-
-
IIL
VI = GND
VO = VCC
VO = GND
-
-
±1
µA
IOZH
IOZL
VIK
IODH
IODL
IOS
-
-
±1
High Impedance Output Current
(3-State Outputs Pins)
VCC= Max.
-
-
±1
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Short Circuit Current
VCC= Min., IIN = –18mA
-
-45
50
-0.7
-74
90
-135
3
-1.2
-180
200
-240
-
V
V
V
V
CC= 3.3V, VIN = VIH or VIL, VO = 1.5V3,4
CC= 3.3V, VIN = VIH or VIL, VO = 1.5V3,4
CC= Max., VO = GND3,4
mA
mA
mA
-60
2.45
2.45
VCC - 0.2
-
IOL= 12mA
VCC= Min.
VOH
Output HIGH Voltage
Output LOW Voltage
V
V
IOH= –8mA
OH= –100µA
3
-
VIN = VIH or VIL
I
-
-
IOL= 12mA
IOL= 8mA
0.3
0.2
0.4
0.4
VCC= Min.
-
VOL
VIN = VIH or VIL
I
OL= 100µA
-
-
0.2
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, 25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC -0.6V at rated current.
3.3V CMOS Dual 1-To-5 Clock Driver
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Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Power Supply Characteristics
Symbol
Parameter
Test Conditions1
Min
Typ2
Max
Unit
ICCL
ICCH
ICCZ
Quiescent Power Supply
Current
VCC = Max. VIN = GND or VCC
-
0.1
30
µA
Power Supply Current per
Input HIGH
VCC = Max.
∆ICC
-
-
45
80
300
120
µA
VIN = VCC –0.6V
VCC= Max.
Dynamic Power Supply
Current per Output3
VIN = VCC
ICCD
CL= 15pF
µA/MHz
V
IN = GND
All Outputs Toggling
VIN = VCC
VCC= Max.
-
-
-
125
125
155
150
150
195
V
IN = GND
CL= 15pF
All Outputs Toggling
fi = 133MHz
V
IN = VCC –0.6V
VIN = GND
Total Power Supply
Current4
IC
mA
VIN = VCC
VCC= Max.
VIN = GND
CL= 15pF
All Outputs Toggling
fi = 166MHz
V
IN = VCC –0.6V
VIN= GND
-
160
195
Notes:
1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
4. IC = IQUIESCENT + IINPUTS + IDYNAMIC
I
C = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ
)
∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
3.3V CMOS Dual 1-To-5 Clock Driver
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Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Switching Characteristics Over Operating Range – ASM2P3805D3,4
Symbol
Parameter
Conditions1
Min2
Max
Unit
tPLH
tPHL
Propagation Delay
1
3
nS
INA to OAn, INB to OBn
Output Rise Time
tR
-
1.5
nS
(Measured from 0.8V to 2V)
Output Fall Time
tF
-
-
-
-
1.5
270
270
550
nS
pS
pS
pS
(Measured from 2V to 0.8V)
tSK(O)
tSK(P)
tSK(PP)
Same device output pin to pin skew5
CL= 15pF
Pulse skew6,9
f≤133MHz
Part to part skew7
Output Enable Time
tPZL
tPZH
tPLZ
tPHZ
-
5.2
nS
¯¯
¯¯
OEA to OAn, OEB to OBn
Output Disable Time
-
-
5.2
nS
¯¯
¯¯
OEA to OAn, OEB to OBn
fMAX
Input Frequency
133
MHz
Switching Characteristics Over Operating Range – ASM2P3805E3,4
Symbol
Parameter
Conditions1,8
Min2
Max
Unit
tPLH
tPHL
Propagation Delay
0.5
2.5
nS
INA to OAn, INB to OBn
Output Rise Time
tR
tF
-
-
1
1
nS
nS
(Measured from 0.7V to 1.7V)
Output Fall Time
(Measured from 1.7V to 0.7V)
tSK(O)
tSK(P)
Same device output pin to pin skew5
-
-
-
200
270
550
pS
pS
pS
CL= 15pF
Pulse skew6,9
f ≤166MHz
tSK(PP)
Part to part skew7
Output Enable Time
tPZL
tPZH
tPLZ
tPHZ
-
5.2
nS
¯¯
¯¯
OEA to OAn, OEB to OBn
Output Disable Time
-
-
5.2
nS
¯¯
¯¯
OEA to OAn, OEB to OBn
fMAX
Input Frequency
166
MHz
Notes:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH , tPHL and tSK(O) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min and Max limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not
imply skew.
5. Skew measured between all outputs under identical transitions and load conditions.
6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions.
7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature.
8. Airflow of 1m/s is recommended for frequencies above 133MHz.
9. This parameter is measured using f = 1MHz.
3.3V CMOS Dual 1-To-5 Clock Driver
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Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Test Circuits and Waveforms
Switch Position
Test
Test Conditions
Symbol
VCC = 3.3V ±0.3V
Unit
pF
Ω
Switch
CL
RT
RL
15
Disable Low
Enable Low
6V
ZOUT of pulse generator
33
Disable High
Enable High
Ω
GND
tR / tF
1 (0V to 3V or 3V to 0V)
nS
Definitions:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
t
R / tF = Rise/Fall time of the input stimulus from the Pulse Generator.
3.3V CMOS Dual 1-To-5 Clock Driver
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Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Test Circuits and Waveforms
3.3V CMOS Dual 1-To-5 Clock Driver
7 of 12
Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Package Information
20-lead SSOP ( 150 mil ) Package
Dimensions
Millimeters
Symbol
Inches
Min
0.053
0.004
….
0.337
0.007
0.228
0.150
0.016
Max
0.069
0.010
0.059
0.344
0.012
0.244
0.157
0.035
Min
1.346
0.102
….
8.560
0.178
5.791
3.810
0.406
Max
1.753
0.254
1.499
8.738
0.274
6.198
3.988
0.890
A
A1
A2
D
c
E
E1
L
L1
b
R1
a
0.010 BASIC
0.254 BASIC
0.203
0.003
0°
0.325
….
8°
0.008
0.08
0°
0.014
…..
8°
e
0.025 BASIC
0.635 BASIC
3.3V CMOS Dual 1-To-5 Clock Driver
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Notice: The information in this document is subject to change without notice.
June 2005
rev 0.2
ASM2P3805X
20-lead QSOP Package
Dimensions
Millimeters
Symbol
Inches
Min
Max
0.068
0.008
0.012
0.010
0.344
0.157
Min
1.52
0.10
0.23
0.18
8.56
3.81
Max
1.73
0.20
0.30
0.25
8.74
3.99
A
A1
b
0.060
0.004
0.009
0.007
0.337
0.150
c
D
E
e
0.025 BSC
0.64 BSC
H
h
L
S
a
0.230
0.010
0.016
0.056
0°
0.244
0.016
0.035
0.060
8°
5.84
0.25
0.41
1.42
0°
6.20
0.41
0.89
1.52
8°
3.3V CMOS Dual 1-To-5 Clock Driver
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Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Ordering Information
Part Number
ASM2P3805DG-20-AR
ASM2P3805DG-20-AT
ASM2P3805DG-20-DR
ASM2P3805DG-20-DT
ASM2I3805DG-20-AR
ASM2I3805DG-20-AT
ASM2I3805DG-20-DR
ASM2I3805DG-20-DT
ASM2P3805EG-20-AR
ASM2P3805EG-20-AT
ASM2P3805EG-20-DR
ASM2P3805EG-20-DT
ASM2I3805EG-20-AR
ASM2I3805EG-20-AT
ASM2I3805EG-20-DR
ASM2I3805EG-20-DT
Marking
2P3805DG
Package Type
20-Pin SSOP, TAPE & REEL, Green
20-Pin SSOP, TUBE, Green
Temperature
Commercial
Commercial
Commercial
Commercial
Industrial
2P3805DG
2P3805DG
2P3805DG
2I3805DG
2I3805DG
2I3805DG
2I3805DG
2P3805EG
2P3805EG
2P3805EG
2P3805EG
2I3805EG
2I3805EG
2I3805EG
2I3805EG
20-Pin QSOP, TAPE & REEL, Green
20-Pin QSOP, TUBE, Green
20-Pin SSOP, TAPE & REEL, Green
20-Pin SSOP, TUBE, Green
Industrial
20-Pin QSOP, TAPE & REEL, Green
20-Pin QSOP, TUBE, Green
Industrial
Industrial
20-Pin SSOP, TAPE & REEL, Green
20-Pin SSOP, TUBE, Green
Commercial
Commercial
Commercial
Commercial
Industrial
20-Pin QSOP, TAPE & REEL, Green
20-Pin QSOP, TUBE, Green
20-Pin SSOP, TAPE & REEL, Green
20-Pin SSOP, TUBE, Green
Industrial
20-Pin QSOP, TAPE & REEL, Green
20-Pin QSOP, TUBE, Green
Industrial
Industrial
3.3V CMOS Dual 1-To-5 Clock Driver
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Notice: The information in this document is subject to change without notice.
June 2005
ASM2P3805X
rev 0.2
Device Ordering Information
A S M 2 P 3 8 0 5 D G - 2 0 - A T
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V CMOS Dual 1-To-5 Clock Driver
11 of 12
Notice: The information in this document is subject to change without notice.
June 2005
rev 0.2
ASM2P3805X
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM2P3805X
Document Version: 0.2
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
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3.3V CMOS Dual 1-To-5 Clock Driver
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