ASM5I2304BG-1H-08-SR [ALSC]
3.3V Zero Delay Buffer; 3.3V零延迟缓冲器
| 型号： | ASM5I2304BG-1H-08-SR |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V Zero Delay Buffer |
| 文件： | 总13页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2005
rev 0.5
ASM5P2304B
3.3V Zero Delay Buffer
Features
has an on-chip PLL, which locks to an input clock,
presented on the REF pin. The PLL feedback is required to
be driven to FBK pin, and can be obtained from one of the
outputs. The input-to-output propagation delay is
guaranteed to be less than 250pS, and the output-to-output
skew is guaranteed to be less than 200pS.
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
Multiple configurations - Refer “ASM5P2304B
Configurations Table”.
Input frequency range: 4MHz to 20MHz
Multiple low-skew outputs.
The ASM5P2304B has two banks of two outputs each.
Multiple ASM5P2304B devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500pS.
Output-output skew less than 200pS.
Device-device skew less than 500pS.
Two banks of four outputs.
Less than 200pS Cycle-to-Cycle jitter
(-1, -1H, -2, -2H).
Available in space saving, 8-pin 150 mil SOIC
Package.
The ASM5P2304B is available in two different
configurations (Refer “ASM5P2304B Configurations Table).
The ASM5P2304B-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2304B-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster. The ASM5P2304B-2 allows the user to
obtain REF and 1/2X or 2X frequencies on each output
bank. The exact configuration and output frequencies
depend on which output drives the feedback pin.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature available.
Functional Description
ASM5P2304B is
a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks in PC,
workstation, datacom, telecom and other high-performance
applications. It is available in an 8 pin package. The part
Block Diagram
FBK
CLKA1
PLL
REF
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
ASM5P2304B Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P2304B-1
ASM5P2304B-1H
ASM5P2304B-2
ASM5P2304B-2
ASM5P2304B-2H
ASM5P2304B-2H
Bank A or Bank B
Bank A or Bank B
Bank A
Reference
Reference
Reference
Reference
Reference
Reference /2
Reference
Bank B
2 X Reference
Reference
Bank A
Reference /2
Reference
Bank B
2 X Reference
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded.
1500
1000
500
0
5
-30
30
-25
10
15
20
25
-20
-15
-10
-5
0
-500
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
To close the feedback loop of the ASM5P2304B, the FBK
pin can be driven from any of the four available output pins.
The output driving the FBK pin will be driving a total load of
7pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining
outputs) can adjust the input output delay. This is shown in
the above graph. For applications requiring zero input-
output delay, all outputs including the one providing
feedback should be equally loaded. If input-output delay
adjustments are required, use the above graph to calculate
loading differences between the feedback output and
remaining outputs. For zero output-output skew, be sure to
load outputs equally.
3.3V Zero Delay Buffer
2 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Pin Configuration
REF
CLKA1
CLKA2
GND
1
2
3
4
8
7
6
5
FBK
VDD
ASM5P2304B
CLKB2
CLKB1
Pin Description for ASM5P2304B
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
REF1
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
Ground
CLKA12
CLKA22
GND
CLKB12
CLKB2 2
VDD
Buffered clock output, bank B
Buffered clock output, bank B
3.3V supply
FBK
PLL feedback input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3.3V Zero Delay Buffer
3 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
Unit
V
VDD + 0.5
7
V
V
Storage Temperature
+150
260
°C
°C
°C
Max. Soldering Temperature (10 sec)
Junction Temperature
150
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2000
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
Operating Conditions for ASM5P2304B Commercial Temperature Devices
Parameter
Description
Min
3.0
0
Max
3.6
70
Unit
V
VDD
TA
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, from 4MHz to 20MHz
Input Capacitance3
°C
CL
30
pF
pF
CIN
7
Electrical Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Test Conditions
Min
Max
Unit
VIL
VIH
IIL
0.8
V
V
2.0
VIN = 0V
50.0
µA
µA
IIH
VIN = VDD
100.0
I
I
I
I
OL = 8mA (-1, -2)
VOL
VOH
Output LOW Voltage4
Output HIGH Voltage4
0.4
V
V
OH = 12mA (-1H, -2H)
OL = -8mA (-1, -2)
OH = -12mA (-1H, -2H)
2.4
IDD
Supply Current
Unloaded outputs, 20MHz REF (-1,-1H, -2,-2H)
10
mA
Note:
3. Applies to both Ref Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
4 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Switching Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
Description
Test Conditions
Min Typ Max Unit
1/t1
Output Frequency
30pF load, -1,-1H,-2, -2H devices
4
20 MHz
Duty Cycle 5= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = 20MHz
40.0 50.0 60.0
45.0 50.0 55.0
%
%
30pF load
Duty Cycle 5 = (t2 / t1) * 100
(-1, -2,-1H, -2H)
Measured at 1.4V, FOUT = <20MHz
15pF load
Measured between 0.8V and 2.0V
Output Rise Time 5
(-1, -2)
t3
t3
t3
t4
t4
t4
2.20 nS
1.50 nS
1.50 nS
2.20 nS
1.50 nS
1.25 nS
30pF load
Output Rise Time 5
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
Measured between 0.8V and 2.0V
Output Rise Time 5
(-1H, -2H)
30pF load
Output Fall Time 5
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
Measured between 2.0V and 0.8V
Output Fall Time 5
(-1, -2)
15pF load
Output Fall Time 5
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
Output-to-output skew on same bank
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
200
200
(-1, -2)
Output-to-output skew (-1H, -2H)
t5
pS
Output bank A -to- output bank B skew
200
(-1, -2H)
Output bank A to output bank b skew
(-2)
All outputs equally loaded
Measured at VDD /2
400
Delay, REF Rising Edge to FBK Rising
t6
t7
t8
0
0
±250 pS
Edge 5
Measured at VDD/2 on the FBK pins of
the device
Device-to-Device Skew 5
Output Slew Rate5
500
pS
Measured between 0.8V and 2.0V using
1
V/nS
Test Circuit #2
Measured at 20MHz, loaded outputs,
15pF load
175
200
100
400
375
1.0
Cycle-to-cycle jitter 5
(-1, -1H, -2H)
Measured at 20MHz, loaded outputs,
tJ
pS
30pF load
Measured at 20MHz, loaded outputs,
15pF load
Measured at 20MHz, loaded outputs,
Cycle-to-cycle jitter 5
(-2)
30pF load
tJ
pS
Measured at 20MHz, loaded outputs,
15pF load
Stable power supply, valid clock
tLOCK
PLL Lock Time 5
mS
presented on REF and FBK pins
Note:
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
5 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Operating Conditions for ASM5I2304B Industrial Temperature Devices
Parameter
Description
Min
3.0
Max
3.6
85
Unit
V
VDD
TA
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, from 4MHz to 20MHz
Input Capacitance6
-40
°C
CL
30
pF
pF
CIN
7
Note:
6. Applies to both Ref Clock and FBK.
Electrical Characteristics for ASM5I2304B Industrial Temperature Devices
Parameter
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Test Conditions
Min
Max
0.8
Unit
V
VIL
VIH
IIL
2.0
V
VIN = 0V
50.0
µA
µA
IIH
VIN = VDD
100.0
I
I
OL = 8mA (-1, -2)
VOL
VOH
Output LOW Voltage7
0.4
V
V
OH = 12mA (-1H, -2H)
I
I
OL = -8mA (-1, -2)
OH = -12mA (-1H, -2H)
Output HIGH Voltage7
2.4
Unloaded outputs, 20MHz REF
(-1, -1H, -2, -2H)
IDD
Supply Current
10
mA
Note:
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
6 of 13
Notice: The information in this document is subject to change without notice.
September 2005
rev 0.5
ASM5P2304B
Switching Characteristics for ASM5I2304B Industrial Temperature Devices
All parameters are specified with loaded outputs
Parameter
Description
Test Conditions
Min Typ Max Unit
t1
Output Frequency
30pF load,-1, -1H,-2, -2H devices
4
20 MHz
Duty Cycle8 = (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <20MHz
40.0 50.0 60.0
45.0 50.0 55.0
%
%
30pF load
Duty Cycle8= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <20MHz
15pF load
Measured between 0.8V and 2.0V
Output Rise Time8
(-1, -2)
t3
t3
t3
t4
t4
t4
2.50 nS
1.50 nS
1.50 nS
2.50 nS
1.50 nS
1.25 ns
200
30pF load
Output Rise Time8
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
Measured between 0.8V and 2.0V
Output Rise Time8
(-1H, -2H)
30pF load
Output Fall Time8
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
Measured between 2.0V and 0.8V
Output Fall Time8
(-1, -2)
15pF load
Output Fall Time8
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
Output-to-output skew on same bank
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at VDD /2
(-1, -2)8
Output-to-output skew
(-1H, -2H)
Output bank A -to- output bank B skew
200
pS
200
t5
(-1, -2H)
Output bank A -to- output bank B skew
(-2)
Delay, REF Rising Edge to FBK Rising
400
t6
t7
t8
0
0
±250 pS
500 pS
V/nS
Edge8
Measured at VDD/2 on the FBK pins of the
device
Device-to-Device Skew 8
Output Slew Rate8
Measured between 0.8V and 2.0V using
1
Test Circuit #2
Measured at 20MHz, loaded outputs,
15pF load
180
Cycle-to-cycle jitter 8
(-1, -1H, -2H)
Measured at 20MHz, loaded outputs,
tJ
pS
pS
200
100
400
380
30pF load
Measured at 20MHz, loaded outputs,
15pF load
Measured at 20MHz, loaded outputs,
Cycle-to-cycle jitter8
(-2)
30pF load
tJ
Measured at 20MHz, loaded outputs,
15pF load
Stable power supply, valid clock presented
tLOCK
PLL Lock Time8
1.0 mS
on REF and FBK pins
Note:
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
7 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Switching Waveforms
Duty Cycle Timing
t1
t 2
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
0.8 V
2.0 V
0.8 V
OUTPUT
t4
t3
Output - Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Input - Output Propagation Delay
VDD /2
INPUT
VDD /2
OUTPUT
t6
Device - Device Skew
/2
VDD
CLKOUT, Device 1
CLKOUT, Device 2
VDD /2
t7
3.3V Zero Delay Buffer
8 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Test Circuits
TEST CIRCUIT # 1
TEST CIRCUIT # 2
VDD
VDD
1KΩ
0.1uF
0.1uF
0.1uF
0.1uF
OUTPUTS
VDD
OUTPUTS
VDD
1KΩ
10pF
CLOAD
GND
GND
GND
GND
For parameter t8 (output skew rate) on -1H devices
3.3V Zero Delay Buffer
9 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Package Information
8-lead (150-mil) SOIC Package
H
E
D
A2
A
C
θ
e
A1
L
B
Dimensions
Symbol
Inches
Millimeters
Min
Max
0.010
0.069
0.059
0.020
0.010
Min
0.10
1.35
1.25
0.31
0.18
Max
0.25
1.75
1.50
0.51
0.25
A1
A
0.004
0.053
0.049
0.012
0.007
A2
B
C
D
E
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
e
H
L
0.016
0°
0.050
8°
0.41
0°
1.27
8°
θ
3.3V Zero Delay Buffer
10 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Ordering Codes
Ordering Code
ASM5P2304B-1-08-SR
ASM5P2304B-1-08-ST
ASM5I2304B-1-08-SR
ASM5I2304B-1-08-ST
ASM5P2304B-1H-08-SR
ASM5P2304B-1H-08-ST
ASM5I2304B-1H-08-SR
ASM5I2304B-1H-08-ST
ASM5P2304B-2-08-SR
ASM5P2304B-2-08-ST
ASM5I2304B-2-08-SR
ASM5I2304B-2-08-ST
ASM5P2304B-2H-08-SR
ASM5P2304B-2H-08-ST
ASM5I2304B-2H-08-SR
ASM5I2304B-2H-08-ST
ASM5P2304BF-1-08-SR
ASM5P2304BF-1-08-ST
ASM5I2304BF-1-08-SR
ASM5I2304BF-1-08-ST
ASM5P2304BF-1H-08-SR
ASM5P2304BF-1H-08-ST
ASM5I2304BF-1H-08-SR
ASM5I2304BF-1H-08-ST
ASM5P2304BF-2-08-SR
ASM5P2304BF-2-08-ST
ASM5I2304BF-2-08-SR
ASM5I2304BF-2-08-ST
ASM5P2304BF-2H-08-SR
ASM5P2304BF-2H-08-ST
ASM5I2304BF-2H-08-SR
ASM5I2304BF-2H-08-ST
ASM5P2304BG-1-08-SR
ASM5P2304BG-1-08-ST
ASM5I2304BG-1-08-SR
ASM5I2304BG-1-08-ST
Marking
5P2304B-1
Package Type
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Operating Range
Commercial
Commercial
Industrial
5P2304B-1
5I2304B-1
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
5I2304B-1
Industrial
5P2304B-1H
5P2304B-1H
5I2304B-1H
5I2304B-1H
5P2304B-2
5P2304B-2
5I2304B-2
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Industrial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
5I2304B-2
Industrial
5P2304B-2H
5P2304B-2H
5I2304B-2H
5I2304B-2H
5P2304BF-1
5P2304BF-1
5I2304BF-1
5I2304BF-1
5P2304BF-1H
5P2304BF-1H
5I2304BF-1H
5I2304BF-1H
5P2304BF-2
5P2304BF-2
5I2304BF-2
5I2304BF-2
5P2304BF-2H
5P2304BF-2H
5I2304BF-2H
5I2304BF-2H
5P2304BG-1
5P2304BG-1
5I2304BG-1
5I2304BG-1
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Industrial
3.3V Zero Delay Buffer
11 of 13
Notice: The information in this document is subject to change without notice.
September 2005
ASM5P2304B
rev 0.5
Ordering Codes (cont’d)
Ordering Code
Marking
Package Type
Operating Range
ASM5P2304BG-1H-08-SR 5P2304BG-1H
8-pin 150-mil SOIC-TAPE & REEL, Green Commercial
ASM5P2304BG-1H-08-ST
ASM5I2304BG-1H-08-SR
ASM5I2304BG-1H-08-ST
ASM5P2304BG-2-08-SR
ASM5P2304BG-2-08-ST
ASM5I2304BG-2-08-SR
ASM5I2304BG-2-08-ST
5P2304BG-1H
5I2304BG-1H
5I2304BG-1H
5P2304BG-2
5P2304BG-2
5I2304BG-2
5I2304BG-2
8-pin 150-mil SOIC-TUBE, Green
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE, Green
Commercial
Industrial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green Commercial
8-pin 150-mil SOIC-TUBE, Green Commercial
8-pin 150-mil SOIC-TAPE & REEL, Green Industrial
8-pin 150-mil SOIC-TUBE, Green Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green Commercial
8-pin 150-mil SOIC-TUBE, Green Commercial
8-pin 150-mil SOIC-TAPE & REEL, Green Industrial
8-pin 150-mil SOIC-TUBE, Green Industrial
ASM5P2304BG-2H-08-SR 5P2304BG-2H
ASM5P2304BG-2H-08-ST
ASM5I2304BG-2H-08-SR
ASM5I2304BG-2H-08-ST
5P2304BG-2H
5I2304BG-2H
5I2304BG-2H
Device Ordering Information
A S M 5 P 2 3 0 4 B F - 0 8 - S R
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V Zero Delay Buffer
12 of 13
Notice: The information in this document is subject to change without notice.
September 2005
rev 0.5
ASM5P2304B
Copyright © Alliance Semiconductor
Alliance Semiconductor Corporation
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Part Number: ASM5P2304B
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Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semicon
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
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3.3V Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
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