ASM5I9774AF-52-ER [ALSC]
Clock Driver;
| 型号： | ASM5I9774AF-52-ER |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Clock Driver |
| 文件： | 总12页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2005
rev 0.3
ASM5I9774A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
The ASM5I9774A features two reference clock inputs and
provides 14 outputs partitioned in 3 banks of 5, 5, and 4
outputs. Bank A and Bank B divide the VCO output by 4 or
8 while Bank C divides by 8 or 12 per SEL(A:C) settings,
see Functional Table. These dividers allow output to input
ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each
LVCMOS compatible output can drive 50Ω series or
parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:28.
Output frequency range: 8.3MHz to 125MHz
Input frequency range: 4.2MHz to 62.5MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 pS max output-output skew
PLL bypass mode
‘SpreadTrak’
Output enable/disable
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 8.3 MHz to 125 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to the feedback output, FB_OUT. The internal
VCO is running at multiples of the input reference clock set
by the feedback divider, see Frequency Table.
Pin compatible with MPC9774 and CY29774AI.
Industrial temperature range: –40°C to +85°C
52Pin 1.0mm TQFP package
RoHS Compliance
Functional Description
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
The ASM5I9774A is
a low-voltage high-performance
125MHz PLL-based zero delay buffer designed for high-
speed clock distribution applications.
Block Diagram
VCO_SEL
PLL_EN
TCLK_SEL
TCLK0
+2
CLK
+2/+4
+2/+4
QA0
QA1
QA2
QA3
QA4
PLL
STOP
TCLK1
200-
+4
FB_IN
500MHZ
SELA
CLK
QB0
QB1
QB2
QB3
QB4
STOP
SELB
CLK
QC0
+4/+6
STOP
QC1
QC2
QC3
SELC
CLK_STP#
FB_OUT
+4/+6/+8/+12
FB_SEL(1.0)
MR#/OE
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005
ASM5I9774A
rev 0.3
Pin Configuration
48
45
43
44 42 41 40
52 51 50 49
47 46
VSS
MR#/OE
CLK_STP#
SELB
1
39
38
37
36
35
34
33
32
31
30
29
28
27
VSS
QB1
2
3
VDDQB
QB2
4
5
SELC
VSS
6
PLL_EN
SELA
QB3
ASM5I9774A
7
VDDQB
QB4
TCLK_SEL
TCLK0
TCLK1
NC
8
9
FB_IN
VSS
10
11
12
13
FB_OUT
VDDFB
NC
VDD
AVDD
18
21
22 23 24
14 15 16 17
19 20
25 26
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
2 of 12
Notice: The information in this document is subject to change without notice.
June 2005
ASM5I9774A
rev 0.3
Pin Description1
Pin
Name
TCLK0
I/O
I, PD
Type
LVCMOS
LVCMOS
Description
LVCMOS/LVTTL reference clock input
LVCMOS/LVTTL reference clock input
9
10
TCLK1
I, PU
16, 18,
QA(4:0)
QB(4:0)
O
LVCMOS
LVCMOS
Clock output bank A
Clock output bank B
Clock output bank C
21, 23, 25
32, 34,
O
36, 38, 40
44, 46,
48, 50
QC(3:0)
O
O
LVCMOS
LVCMOS
29
FB_OUT
Feedback clock output. Connect to FB_IN for normal operation.
Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference
clock. See Table 1.
31
FB_IN
I, PU
LVCMOS
2
MR#/OE
I, PU
I, PU
I, PU
I, PD
I, PD
I, PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDD
Output enable/disable input. See Table 2.
Clock stop enable/disable input. See Table 2.
PLL enable/disable input. See Table 2.
Reference select input. See Table 2.
3
CLK_STP#
PLL_EN
6
8
TCLK_SEL
VCO_SEL
SEL(A:C)
52
VCO divider select input. See Table 2.
7, 4, 5
20, 14
Frequency select input, Bank (A:C). See Table 3.
Feedback dividers select input. See Table 4.
2.5V or 3.3V Power supply for bank A output clocks2,3
2.5V or 3.3V Power supply for bank B output clocks2,3
2.5V or 3.3V Power supply for bank C output clocks2,3
2.5V or 3.3V Power supply for feedback output clock2,3
2.5V or 3.3V Power supply for PLL2,3
FB_SEL(1,0) I, PD
17, 22, 26 VDDQA
33, 37, 41 VDDQB
Supply
Supply
Supply
Supply
Supply
Supply
Supply
VDD
45, 49
28
VDDQC
VDDFB
AVDD
VDD
VDD
VDD
13
VDD
12
VDD
2.5V or 3.3V Power supply for core and inputs2,3
15
AVSS
Ground
Analog Ground
1, 19, 24,
30, 35,
39, 43,
47, 51
VSS
Supply
Ground
Common Ground
No Connection
11, 27, 42 NC
Note: 1.PU = Internal pull up, PD = Internal pull down.
2.A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the
pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB
power supply pins
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
3 of 12
Notice: The information in this document is subject to change without notice.
June 2005
rev 0.3
ASM5I9774A
‘SpreadTrak’
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM59774A is designed so as not to filter off the Spread
Spectrum feature of the Reference Input, assuming it
exists.
When a zero delay buffer is not designed to pass the
Spread Spectrum feature through, the result is
a
significant amount of tracking skew which may cause
problems in the systems requiring synchronization.
Table 1. Frequency Table
Feedback Output
Divider
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
VCO
(AVDD = 2.5V)
25 MHz to 50 MHz
÷8
Input Clock * 8
Input Clock * 12
Input Clock * 16
Input Clock * 24
Input Clock * 32
Input Clock * 48
25 MHz to 62.5 MHz
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
4.2 MHz to 10.4 MHz
÷12
÷16
÷24
÷32
÷48
16.6 MHz to 33.3 MHz
12.5 MHz to 25 MHz
8.3 MHz to 16.6 MHz
6.25 MHz to 12.5 MHz
4.2 MHz to 8.3 MHz
Table 2. Function Table (configuration controls)
Control
TCLK_SEL
VCO_SEL
Default
0
1
0
0
TCLK0
TCLK1
VCO÷2 (high input frequency range)
VCO÷4 (low input frequency range)
Bypass mode, PLL disabled. The input clock
PLL enabled. The VCO output
connects to the output dividers
PLL_EN
1
1
1
connects to the output dividers
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL
feedback loop is open and the VCO running at its
minimum frequency. The device is reset by the
internal power-on reset (POR) circuitry during
power-up.
MR#/OE
Outputs enabled
Outputs enabled
QA, QB, and QC outputs disabled in LOW state.
CLK_STP#
FB_OUT is not affected by CLK_STP#.
Table 3. Function Table (Bank A, B and C)
VCO_SEL
SELA
QA(4:0)
÷4
SELB
QB(4:0)
÷4
SELC
QC(3:0)
÷8
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷8
÷16
÷8
÷8
÷16
÷12
÷16
÷24
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
4 of 12
Notice: The information in this document is subject to change without notice.
June 2005
ASM5I9774A
rev 0.3
Table 4. Function Table (FB_OUT)
VCO_SEL
FB_SEL1
FB_SEL0
FB_OUT
÷8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷16
÷12
÷24
÷16
÷32
÷24
÷48
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Condition
Min
–0.3
2.375
–0.3
–0.3
-
200
-
–65
–40
-
Max
5.5
Unit
V
V
V
V
Functional
Relative to VSS
Relative to VSS
3.465
VDD+ 0.3
VDD+ 0.3
VDD ÷2
-
150
+150
+85
VOUT
VTT
LU
RPS
TS
V
Functional
mA
mVp-p
°C
°C
°C
Ripple Frequency < 100 kHz
Non Functional
Functional
TA
TJ
Functional
150
ØJC
ØJA
ESDH
FIT
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Functional
Functional
-
-
23
55
-
°C/W
°C/W
Volts
ppm
2000
Manufacturing test
10
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
5 of 12
Notice: The information in this document is subject to change without notice.
June 2005
ASM5I9774A
rev 0.3
DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
Description
Condition
Min
Typ
Max
0.7
VDD+0.3
0.6
Unit
V
V
V
V
µA
µA
VIL
VIH
VOL
VOH
IIL
Input Voltage, Low
LVCMOS
-
1.7
-
1.8
-
-
-
-
-
-
-
Input Voltage, High
LVCMOS
1
Output Voltage, Low
Output Voltage, High
IOL= 15mA
IOH= –15mA
VIL= VSS
1
-
2
Input Current, Low
–100
100
2
IIH
Input Current, High
VIL= VDD
-
IDDA
IDDQ
IDD
CIN
ZOUT
PLL Supply Current
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
-
-
-
-
14
5
-
135
4
10
8
-
-
22
mA
mA
mA
pF
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
18
Ω
Note: 1. Driving one 50Ωparallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output
terminated transmission lines
drives up to two 50 Ωseries-
2. Inputs have pull-up or pull-down resistors that affect the input current.
DC Electrical Specifications (VDD= 3.3V ± 5%, TA= –40°C to +85°C)
Parameter
VIL
VIH
Description
Condition
LVCMOS
LVCMOS
IOL= 24 mA
IOL= 12 mA
IOH= –24 mA
VIL= VSS
Min
Typ
Max
0.8
VDD + 0.3
0.55
Unit
V
V
Input Voltage, Low
-
-
-
-
-
-
-
-
Input Voltage, High
2.0
-
-
2.4
-
-
VOL
Output Voltage, Low1
V
0.30
-
–100
100
VOH
IIL
IIH
Output Voltage, High1
Input Current, Low2
Input Current, High2
V
µA
µA
VIL= VDD
IDDA
IDDQ
IDD
CIN
ZOUT
PLL Supply Current
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
-
-
-
-
12
5
-
225
4
10
8
-
-
18
mA
mA
mA
pF
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
15
Ω
Note: 1. Driving one 50Ωparallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output
terminated transmission lines
drives up to two 50 Ωseries-
2. Inputs have pull-up or pull-down resistors that affect the input current.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
6 of 12
Notice: The information in this document is subject to change without notice.
June 2005
ASM5I9774A
rev 0.3
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)1
Parameter
fVCO
Description
VCO Frequency
Condition
Min
200
25
Typ
Max
400
50
Unit
MHz
-
-
-
-
-
-
-
÷8 Feedback
÷12 Feedback
÷16 Feedback
÷24 Feedback
÷32 Feedback
÷48 Feedback
16.6
12.5
8.3
33.3
25
16.6
12.5
8.3
fin
Input Frequency
MHz
6.3
4.2
Bypass mode
0
-
200
(PLL_EN = 0)
frefDC
tr, tf
Input Duty Cycle
25
–
-
-
-
-
-
-
-
-
-
75
1.0
100
50
%
TCLK Input Rise/FallTime
0.7V to 1.7V
÷4 Output
nS
50
÷8 Output
25
fMAX
Maximum Output Frequency
MHz
÷12 Output
÷16 Output
÷24 Output
16.6
12.5
8.3
45
33.3
25
16.6
55
DC
tr, tf
Output Duty Cycle
%
Output Rise/Fall times
0.7V to 1.8V
0.1
0.75
nS
Propagation Delay
(static phase offset)
TCLK to FB_IN, does
not include jitter
t(φ)
–100
-
100
pS
pS
tsk(O)
Output-to-Output Skew
Skew within Bank
-
-
-
-
150
150
Banks at same
frequency
tsk(B)
Bank-to-Bank Skew
pS
Banks at different
frequency
-
-
200
tPLZ, HZ
tPZL, ZH
Output Disable Time
Output Enable Time
-
-
-
-
10
10
nS
nS
PLL Closed Loop Bandwidth
BW
-
0.5 -1.0
-
MHz
(–3 dB)
Same frequency
-
-
-
-
-
-
-
-
-
-
100
250
100
125
1
tJIT(CC)
Cycle-to-Cycle Jitter
pS
Multiple frequencies
tJIT(PER)
tJIT(φ)
Period Jitter
pS
pS
I/O Phase Jitter
tLOCK
Maximum PLL Lock Time
mS
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
7 of 12
Notice: The information in this document is subject to change without notice.
June 2005
ASM5I9774A
rev 0.3
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)1
Parameter
fVCO
fin
Description
VCO Frequency
Input Frequency
Condition
Min
200
25
Typ
Max
500
Unit
MHz
-
-
-
-
-
-
-
÷8 Feedback
62.5
÷12 Feedback
÷16 Feedback
÷24 Feedback
÷32 Feedback
÷48 Feedback
16.6
12.5
8.3
41.6
31.25
20.8
MHz
6.25
4.2
15.625
10.4
Bypass mode
0
-
200
(PLL_EN = 0)
frefDC
Input Duty Cycle
25
-
-
-
-
-
-
-
-
75
1.0
%
tr, tf
fMAX
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8V to 2.0V
÷4 Output
nS
50
25
125
62.5
41.6
31.25
20.8
55
÷8 Output
MHz
÷12 Output
÷16 Output
÷24 Output
16.6
12.5
8.3
45
DC
Output Duty Cycle
%
tr, tf
t(φ)
Output Rise/Fall times
0.8V to 2.4V
0.1
1.0
nS
Propagation Delay (static phase
offset)
TCLK to FB_IN, same
–100
-
-
-
100
150
150
pS
pS
VDD, does not include jitter
tsk(O)
tsk(B)
Output-to-Output Skew
Bank-to-Bank Skew
Skew within Bank
-
-
Banks at same voltage,
same frequency
Banks at same voltage,
different frequency
pS
-
-
225
Banks at different voltage
-
-
-
-
-
-
250
10
tPLZ, HZ
Output Disable Time
Output Enable Time
nS
nS
tPZL, ZH
BW
10
PLL Closed Loop Bandwidth
-
0.5 - 1.0
-
MHz
(–3dB)
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
-
-
-
-
-
-
-
-
-
-
150
300
100
150
1
pS
Multiple frequencies
tJIT(PER)
tJIT(φ)
Period Jitter
pS
pS
I/O Phase Jitter
I/O at same VDD
tLOCK
Maximum PLL Lock Time
mS
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
8 of 12
Notice: The information in this document is subject to change without notice.
June 2005
rev 0.3
ASM5I9774A
Zo = 50 ohm
RT = 50 ohm
Pulse
Generator
Z = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V
VDD
LVCMOS_CLK
VDD/2
GND
VDD
VDD/2
t(φ)
GND
Figure 2. LVCMOS Propagation Delay t(φ), Static Phase Offset
VDD
VDD/2
GND
tP
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (DC)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(0)
Figure 4. Output-to-Output Skew, tsk(O)
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
9 of 12
Notice: The information in this document is subject to change without notice.
June 2005
ASM5I9774A
rev 0.3
Package Information
52-lead TQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Millimeters
Min
….
Max
Min
…
0.05
0.95
11.8
9.9
11.8
9.9
0.45
Max
1.2
A
A1
A2
D
D1
E
0.0472
0.0059
0.0413
0.4803
0.3976
0.4803
0.3976
0.0295
0.0020
0.0374
0.4646
0.3898
0.4646
0.3898
0.0177
0.15
1.05
12.2
10.1
12.2
10.1
0.75
E1
L
L1
T
T1
b
b1
R0
a
0.03937 REF
1.00 REF
0.0035
0.0038
0.0102
0.0106
0.0031
0°
0.0079
0.0062
0.0150
0.0130
0.0079
7°
0.09
0.097
0.26
0.27
0.08
0°
0.2
0.157
0.38
0.33
0.2
7°
e
0.0256 BASE
0.65 BASE
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
10 of 12
Notice: The information in this document is subject to change without notice.
June 2005
ASM5I9774A
rev 0.3
Ordering Information
Part Number
ASM5I9774A-52-ET
ASM5I9774A-52-ER
ASM5I9774AG-52-ET
Marking
ASM5I9774A
ASM5I9774A
ASM5I9774AG
Package Type
52-pin TQFP, Tray
52-pin TQFP – Tape and Reel
52-pin TQFP, Tray, Green
Operating Range
Industrial
Industrial
Industrial
ASM5I9774AG-52-ER ASM5I9774AG
52-pin TQFP – Tape and Reel, Green
Industrial
Device Ordering Information
A S M 5 I 9 7 7 4 A G - 5 2 - E T
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
11 of 12
Notice: The information in this document is subject to change without notice.
June 2005
rev 0.3
ASM5I9774A
Copyright © Alliance Semiconductor
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
All Rights Reserved
Part Number: ASM5I9774A
Document Version: 0.3
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
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including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
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2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
12 of 12
Notice: The information in this document is subject to change without notice.
相关型号：
ASM5I9774AG-52-ER
PLL Based Clock Driver, 9774 Series, 14 True Output(s), 0 Inverted Output(s), PQFP52, 1 MM HEIGHT, GREEN, TQFP-52
PULSECORE
ASM5I9774AG-52-ET
PLL Based Clock Driver, 9774 Series, 14 True Output(s), 0 Inverted Output(s), PQFP52, 1 MM HEIGHT, GREEN, TQFP-52
PULSECORE
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