ASM707EPA [ALSC]
Low Power UP Supervisor Circuits; 低功耗UP监控电路
| 型号： | ASM707EPA |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Low Power UP Supervisor Circuits |
| 文件： | 总15页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Low Power µP Supervisor Circuits
General Description
Features
•
Precision power supply monitor
The ASM705 / 706 / 707 / 708 and AS813L are cost effective
CMOS supervisor circuits that monitor power-supply and
battery voltage level, and µP/µC operation.
•4.65V threshold (ASM705/707/813L)
•4.40V threshold (ASM706/708)
Debounced manual reset input
Voltage monitor
•
•
The family offers several functional options. Each device
generates a reset signal during power-up, power-down and
during brownout conditions. A reset is generated when the
supply drops below 4.65V (ASM705/707/813L) or 4.40V
(ASM706/708). For 3V power supply applications, refer to the
ASM705P/R/S/T data sheet. In addition, the ASM705/706/813L
feature a 1.6 second watchdog timer. The ASM707/708 have
both active-HIGH and active-LOW reset outputs but no
watchdog function. The ASM813L has the same pin-out and
functions as the ASM705 but has an active-HIGH reset output.
A versatile power-fail circuit has a 1.25V threshold, useful in low
battery detection and for monitoring non-5V supplies. All
devices have a manual reset (MR) input. The watchdog timer
output will trigger a reset if connected to MR.
•1.25V threshold
•Battery monitor / Auxiliary supply monitor
Watchdog timer (ASM705/706/813L)
200ms reset pulse width
•
•
•
•
Active HIGH reset output (ASM707/708/813L)
MicroSO package
Applications
•
•
•
•
•
•
•
Computers and embedded controllers
Portable/Battery-operated systems
Intelligent instruments
Wireless communication systems
PDAs and hendheld equipment
Automative Systems
Safety Systems
All devices are available in 8-pin DIP, SO and MicroSO
packages.
Typical Operating Circuit
Unregulated DC
+5V Regulator
µP
VCC
R1
VCC
RESET
RESET
(RESET)
(RESET)
PFI
WDI
I/O LINE
ASM705
ASM706
(ASM813L)
NMI
WDO
PFO
R2
MR
INTERRUPT
Alliance Semiconductor
2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Block Diagrams
Transition
Detector
Watchdog
Timer
WDI
MR
WDO
RESET
V
CC
V
CC
Timebase
0.25mA
0.25mA
RESET
Generator
RESET
RESET
Generator
MR
RESET
(RESET) ASM813L
+
-
V
+
CC
V
CC
-
+
4.65V (ASM707)
4.40V (ASM708)
+
4.65V (ASM705/813L)
4.40V (ASM706)
PFI
PFI
+
-
+
PFO
PFO
-
ASM705
ASM706
ASM813L
1.25V
1.25V
ASM707
ASM708
GND
GND
Pin Configuration
MicroSO
DIP/SO
8
8
RESET
1
NC
RESET (RESET)
WDO
1
WDI
8
8
1
1
2
3
RESET
MR
MR
WDO
ASM705
ASM706
ASM705
ASM706
2
3
ASM707
ASM708
VCC
VCC
7
6
5
2
3
(RESET)
RESET
7
6
5
2
3
RESET
PFO
PFI
RESET
NC
PFO
PFI
7
6
7
6
5
ASM707
ASM708
MR
MR
GND
PFI
WDI
PFO
GND
PFI
(ASM813L)
(ASM813L)
VCC
VCC
GND
4
GND
4
5
4
4
PFO
2 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Pin Description
Pin Number
ASM707/708
ASM705/706
ASM813L
Name
Function
DIP/
DIP/
SO
DIP/
SO
MicroSO
SO
MicroSO
MicroSO
Manual reset input. The active LOW input triggers a reset
pulse. A 250 µA pull-up current allows the pin to be
driven by TTL/CMOS logic or shorted to ground with a
switch.
1
3
1
3
1
3
MR
VCC
2
3
4
5
2
3
4
5
2
3
4
5
+5V power supply input.
GND
Ground reference for all signals.
Power-fail input voltage monitor. With PFI less than
1.25V, PFO goes LOW. Connect PFI to Ground or VCC
4
5
6
7
4
5
6
7
4
5
6
7
PFI
when not in use.
Power-fail output. The output is active LOW and sinks
current when PFI is less than 1.25V.
PFO
Watchdog input. WDI controls the internal watchdog
timer. A HIGH or LOW signal for 1.6sec at WDI allows
the internal timer to run-out, setting WDO LOW. The
watchdog function is disabled by floating WDI or by con-
necting WDI to a high impedance three-state buffer. The
internal watchdog timer clears when: RESET is asserted;
WDI is three-stated ; or WDI sees a rising or falling edge.
6
8
-
-
6
8
WDI
-
-
6
7
8
1
-
-
-
-
NC
Not Connected
Active LOW reset output. Pulses LOW for 200ms when
triggered, and stays LOW whenever VCC is below the
reset threshold. RESET remains LOW for 200ms after
7
1
RESET
V
CC rises above the reset threshold or MR goes from
LOW to HIGH. A watchdog timeout will not trigger
RESET unless WDO is connected to MR.
Watchdog output. WDO goes LOW when the 1.6 second
internal watchdog timer times-out and does not go HIGH
until the watchdog is cleared. In addition, when VCC falls
8
-
2
-
-
-
8
7
2
1
WDO
below the reset threshold, WDO goes LOW. Unlike
RESET, WDO does not have a minimum pulse width and
as soon as VCC exceeds the reset threshold, WDO goes
HIGH with no delay.
Active HIGH reset output. The inverse of RESET. The
ASM813L has only a RESET output.
8
2
RESET
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Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
V
Detailed Description
RT
A
proper reset input enables
a
microprocessor
/
5V
0V
5V
V
CC
microcontroller to start in a known state. ASM70X and
ASM813L assert reset to prevent code execution errors
during power-up, power-down and brown-out conditions.
t
RS
t
RS
RESET
0V
RESET/RESET Timing
The RESET/RESET signals are designed to start a µP/µC in
a known state or return the system to a known state.
5V
0V
MR externally
set low
MR
t
MD
t
MR
The ASM707/708 have two reset outputs, one active-HIGH
RESET and one active-LOW RESET output. The ASM813L
has only an active-HIGH output. RESET is simply the
complement of RESET.
5V
0V
WDO
Figure 1: WDI Three-state operation
RESET is guaranteed to be LOW with VCC above 1.2V.
During a power-up sequence, RESET remains low until the
supply rises above the threshold level, either 4.65V or 4.40V.
RESET goes high approximately 200ms after crossing the
threshold.
Manual Reset (MR)
The active-LOW manual reset input is pulled high by a 250µA
pull-up current and can be driven low by CMOS/TTL logic or
a mechanical switch to ground. An external debounce circuit
is unnecessary since the 140ms minimum reset time will
debounce mechanical pushbutton switches.
During power-down, RESET goes LOW as VCC falls below
the threshold level and is guaranteed to be under 0.4V with
V
CC above 1.2V.
By connecting the watchdog output (WDO) and MR, a
watchdog timeout forces RESET to be generated. The
ASM813L should be used when an active-HIGH RESET is
required.
In a brownout situation where VCC falls below the threshold
level, RESET pulses low. If a brownout occurs during an
already initiated reset, the pulse will continue for a minimum
of 140ms.
Watchdog Timer
The watchdog timer available on the ASM705/706/813L
monitors µP/µC activity. An output line on the processor is
used to toggle the WDI line. If this line is not toggled within
1.6 seconds, the internal timer puts the watchdog output,
WDO, into a LOW state. WDO will remain LOW until a toggle
is detected at WDI.
Power Failure Detection With Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point
and uncommitted output (PFO) and noninverting input (PFI).
This comparator can be used as a supply voltage monitor
with an external resistor voltage divider. The attenuated
voltage at PFI should be set just below the 1.25 threshold. As
the supply level falls, PFI is reduced causing the PFO output
to transit LOW. Normally PFO interrupts the processor so the
system can be shut down in a controlled manner.
If WDI is floated or connected to a three-stated circuit, the
watchdog function is disabled, meaning, it is cleared and not
counting. The watchdog timer is also disabled if RESET is
asserted. When RESET becomes inactive and the WDI input
sees a high or low transition as short as 50ns, the watchdog
timer will begin
a
1.6 second countdown. Additional
4 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
transitions at WDI will reset the watchdog timer and initiate a
new countdown sequence.
BUF
Buffered
RESET
WDO will also become LOW and remain so, whenever the
supply voltage, VCC , falls below the device threshold level.
VCC
WDO goes HIGH as soon as VCC transitions above the
threshold. There is no minimum pulse width for WDO as
there is for the RESET outputs. If WDI is floated, WDO
essentially acts as a low-power output indicator.
µC or µP
ASM70x
RESET
GND
Supply Voltage
4.7kΩ
RESET
Input
GND
WDI
Bi-directional I/O Pin
Figure 3: Bi-directional Reset Pin Interfacing
Monitoring Voltages Other Than VCC
WDO
The ASM705-708 can monitor voltages other than VCC using
the Power Fail circuitry. If a resistive divider is connected
from the voltage to be monitored to the Power Fail input
(PFI), the PFO will go LOW if the voltage at PFI goes below
1.25V reference. Should hysteresis be desired, connect a
resistor (equal to approximately 10 times the sum of the two
resistors in the divider) between the PFI and PFO pins. A
capacitor between PFI and GND will reduce circuit sensitivity
to input high-frequency noise. If it is desired to assert a
RESET for voltages other than VCC then the PFO output is to
RESET
RESET
Figure 2: Watchdog Timing
be connected to the MR.
Application Information
VIN
Ensuring That RESET is Valid Down to VCC = 0V
+5V
When VCC falls below 1.1V, the ASM705-708 RESET output
VCC
no longer pulls down; it becomes indeterminate. To avoid the
possibility that stray charges build up and force RESET to the
wrong state, a pull-down resistor should be connected to the
RESET pin, thus draining such charges to ground and
holding RESET low. The resistor value is not critical. A 100kΩ
resistor will pull RESET to ground without loading it.
R1
MR
ASM70X
PFO
PFI
RESET
To µP
R2
GND
Bi-directional Reset Pin Interfacing
The ASM705/6/7/8 can interface with µP/µC bi-directional
reset pins by connecting a 4.7kΩ resistor in series with the
RESET output and the µP/µC bi-directional RESET pin.
Figure 4: Monitoring +5V and an additional supply VIN
5 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Monitoring a Negative Voltage
VCC
The Power-Fail circuitry can also monitor a negative supply
rail. When the negative rail is OK, PFO will be LOW, and
when the negative rail is failing (not negative enough), PFO
goes HIGH (the opposite of when positive voltages are
monitored). To trigger a reset, these outputs need to be
inverted: adding the resistors and transistor as shown
achieves this. The RESET output will then have the same
sense as for positive voltages: good = HIGH, bad = LOW. It
should be noted that this circuit’s accuracy depends on the
+
R1
R3
VCC
MR
R4
2N3904
ASM70X
PFO
PFI
R2
VCC line, the PFI threshold tolerance, and the resistors.
RESET
To µP
- 1.25
GND
V
1.25 - VTRIP
CC
=
Negative Input Voltage
R
2
R
1
Figure 5: Monitoring a negative voltage
6 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Pin Terminal Voltage with Respect to Ground
V
-0.3
-0.3
6.0
V
V
CC
1
V
+ 0.3
All other inputs
CC
Input Current at V and GND
20
20
mA
mA
V/µs
CC
Output Current: All outputs
Rate of Rise at V
100
CC
Plastic DIP Power Dissipation
(Derate 9mW/°C above 70°C)
700
470
330
mV
mW‘
mW
SO Power Dissipation
(Derate 5.9mW/°C above 70°C)
MicroSO Power Dissipation
(Derate 4.1mW/°C above 70°C)
Operating Temperature Range
ASM705E/706E/707E/708E/813LE
ASM706C/707C/708C/813LC
Storage Temperature Range
Lead Temperature (Soldering 10sec)
Note:
-40
0
+85
70
°C
°C
°C
°C
-65
160
300
1. The input voltage limits of PFI and MR can be exceeded if the input current is less than 10mA.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for pro-
longed time periods may affect device reliability.
7 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Electrical Characteristics
Unless otherwise noted, specifications are over the operating temperature range and VCC supply voltages are 2.7V to 5.5V (ASM706P,
ASM708R), 3.0 V to 5.5V (ASM706/708S), 3.15V to 5.5V (ASM706/708T) and 4.1V to 5.5.V (ASM706/708J)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ASM705/6/7/8C
ASM813L
1.2
1.1
1.2
5.5
5.5
Operating Voltage
Range
VCC
V
ASM705/6/7/8E, ASM813E
ASM705/706C/813LC
ASM705E/706E/813LE
ASM707C/708C
5.5
75
75
140
140
140
140
4.75
4.50
Supply Current
ICC
µA
50
ASM707E/708E
50
ASM705/707/813L, Note 1
ASM706/708 Note 1
4.50
4.25
4.65
4.40
VRT
RESET Threshold
V
RESET Threshold
Hysteresis
Note 1
Note 1
40
mV
tRS
tMR
RESET Pulse Width
MR Pulse Width
140
200
280
ms
µs
0.15
MR to RESET Out
Delay
tMD
Note 1
0.25
µs
VIH
VIL
2.0
MR Input Threshold
MR Pullup current
V
0.8
MR = 0V
100
250
600
µA
ISOURCE = 800µA
VCC - 1.5
RESET Output Voltage
ISINK = 3.2mA
0.4
0.3
V
ASM705/5/7/8, VCC = 1.2V, ISINK = 100µA
ASM707/8/813L, ISOURCE = 800µA
ASM707/8, ISINK = 1.2mA
ASM813L, ISINK =3.2mA
ASM813L, VCC = 1.2V, ISOURCE = 4µA
VCC-1.5
0.4
0.4
RESET Output Voltage
V
0.9
8 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
s
Watchdog Timeout
Period
tWD
ASM705/6/813L
VIL = 0.4V, VIH=0.8VCC
1.00
1.60
2.25
tWP
VIH
VIL
,
WDI Pulse Width
50
ns
3.5
ASM705/706/813L, VCC = 5V
ASM705/6/813L, WDI = VCC
WDI Input Threshold
V
µA
V
0.8
50
150
WDI Input Current
ASM705/6/813L, WDI = 0V
-150
-50
VOH
VOL
ASM705/6/813L, ISOURCE = 800µA
ASM705/6/813L, ISINK = 1.2mA
VCC - 1.5
WDO Output Voltage
0.4
1.3
25
VCC = 5V
PFI Input Threshold
PFI Input Current
1.2
-25
1.25
0.01
V
nA
VOH
VOL
ISOURCE = 800µA
ISINK = 3.2mA
VCC - 1.5
PFO Output Voltage
V
0.4
Notes 1: RESET (ASM705/6/7/8), RESET(ASM707/8, ASM813L)
9 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Package Dimensions
8-Pin MicroSO
D
E
E1
A2
A
a
C
0.10mm
0.004in
e
A1
L
b
Inches
Millimeteres
Min
Min
-
Max
Max
0.10
0.15
0.95
0.40
0.23
3.10
A
A1
A2
b
0.0433
0.0059
0.0374
0.0157
0.0091
0.1220
-
0.0020
0.0295
0.0098
0.0051
0.1142
0.050
0.75
0.25
0.13
2.90
C
D
e
0.0256 BSC
0.193 BSC
0.65 BSC
4.90 BSC
E
E1
L
0.1142
0.1220
0.0276
6°
2.90
0.40
0°
3.10
0.70
6°
0.0157
0°
a
10 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Package Dimensions (contd)
Plastic DIP (8-Pin)
D1
E
D
E1
A1
A
0° -15°
L
b2
eC
eA
e
b
eB
Inches
Millimeteres
Min
Max
Min
Max
A
A1
A2
b
-
0.210
-
-
5.33
0.015
0.115
0.014
0.045
0.030
0.355
0.005
0.300
0.240
0.100
0.300
-
0.38
2.92
0.36
1.14
0.80
9.02
0.13
7.62
6.10
2.54
7.62
-
-
0.195
0.022
0.070
0.045
0.400
-
4.95
0.56
1.78
1.14
10.16
-
b2
b3
D
D1
E
0.325
0.280
-
8.26
7.11
E1
e
eA
eB
eC
L
-
0.430
0.060
0.150
10.92
3.81
-
0.115
2.92
11 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Package Dimensions (contd)
SO (8-Pin)
Inches
Millimeteres
Min Max
Min
Max
0.069
0.010
0.020
0.010
A
A1
B
0.053
0.004
0.013
0.007
1.35
0.10
0.33
0.19
1.75
0.25
0.51
0.25
C
e
0.050
1.27
E
0.150
0.228
0.016
0.189
0.157
0.244
0.050
0.197
3.80
5.80
0.40
4.80
4.00
6.20
1.27
2.00
H
L
D
12 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Ordering Codes
Part Number
Reset Threshold (V)
Temperature Range
Pins-Package
ASM705 Active LOW Reset, Watchdog Output And Manual RESET
ASM705CPA
ASM705CSA
ASM705CUA
ASM705EPA
ASM705ESA
ASM705EUA
4.65
4.65
4.65
4.65
4.65
4.65
0°C to +70 °C
0°C to +70 °C
0°C to +70 °C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8-Plastic DIP
8-SO
8-MicroSO
8-Plastic DIP
8-SO
8-MicroSO
ASM706 Active LOW Reset, Watchdog Output And Manual RESET
ASM706CPA
ASM706CSA
ASM706CUA
ASM706EPA
ASM706ESA
4.40
4.40
4.40
4.40
4.40
0°C to +70 °C
0°C to +70 °C
0°C to +70 °C
-40°C to +85°C
-40°C to +85°C
8-Plastic DIP
8-SO
8-MicroSO
8-Plastic DIP
8-SO
ASM707 Active LOW & HIGH Reset with Manual RESET
ASM707CPA
ASM707CSA
ASM707CUA
ASM707EPA
ASM707ESA
4.65
4.65
4.65
4.65
4.65
0°C to +70 °C
0°C to +70 °C
0°C to +70 °C
-40°C to +85°C
-40°C to +85°C
8-Plastic DIP
8-SO
8-MicroSO
8-Plastic DIP
8-SO
ASM708Active LOW & HIGH Reset with Manual RESET
ASM708CPA
ASM708CSA
ASM708CUA
ASM708EPA
ASM708ESA
4.40
4.40
4.40
4.40
4.40
0°C to +70 °C
0°C to +70 °C
0°C to +70 °C
-40°C to +85°C
-40°C to +85°C
8-Plastic DIP
8-SO
8-MicroSO
8-Plastic DIP
8-SO
ASM813L Active HIGH Reset, Watchdog Output And Manual RESET
ASM813LCPA
ASM813LCSA
ASM813LCUA
ASM813LEPA
ASM813LESA
4.65
4.65
4.65
4.65
4.65
0°C to +70 °C
0°C to +70 °C
0°C to +70 °C
-40°C to +85°C
-40°C to +85°C
8-Plastic DIP
8-SO
8-MicroSO
8-Plastic DIP
8-SO
13 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
July 2004
rev 1.2
Feature Summary
ASM705
ASM706
ASM707
ASM708
ASM813L
Power fail detector
Brownout detection
Manual RESET input
Power-up/down RESET
Watchdog Timer
Active HIGH RESET output
Active LOW RESET output
RESET Threshold (V)
4.65
4.40
4.65
4.40
4.65
14 of 15
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
ASM705 / 706 / 707 / 708
ASM813L
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number:ASM705 / 706 / 707 / 708
ASM813L
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Document Version: 1.2
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or
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