P1766C-08TT [ALSC]
PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8;
| 型号： | P1766C-08TT |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：47K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Specification
P1727/66
Low Power Notebook LCD Panel EMI Reduction IC
FEATURES
•
•
•
•
Low inherent cycle-to-cycle jitter
3.3V operating voltage
•
•
FCC approved method of EMI attenuation
Generates a low EMI spread spectrum of
the input clock frequency
CMOS/TTL compatible inputs and outputs
Ultra low power CMOS design
TBD mA @3.3V, 54 MHz
TBD mA @3.3V, 65 MHz
•
Optimized for frequency range:
P1727X: 20MHz to 40MHz
P1766X: 40MHz to 80MHz
•
Supports notebook VGA and other LCD
timing controller applications
•
•
Internal loop filter minimizes external
components and board space
•
•
Available in 8 pin SOIC and TSSOP
8 different frequency deviations ranging
Qualified for Industrial Temp Spec. (+85C)
from +/-0.625% to –3.50%
The P1727/66 uses the most efficient and
optimized modulation profile approved by the
FCC and is implemented by using a proprietary
all-digital method.
PRODUCT DESCRIPTION
The P1727/66 is a versatile spread spectrum
frequency modulator designed specifically for a
wide range of clock frequencies. The P1727/66
reduces electromagnetic interference (EMI) at
the clock source, allowing system wide
reduction of EMI of down stream (clock and
data dependent signals). The P1727/66 allows
significant system cost savings by reducing the
number of circuit board layers and shielding that
are traditionally required to pass EMI
regulations.
APPLICATIONS
The P1727/66 is targeted towards notebook
LCD displays, other displays using an LVDS
interface, PC peripheral devices, and embedded
systems.
Figure 1 – P1727/66 Pin Diagram
The P1727/66 modulates the output of a single
PLL in order to “spread” the bandwidth of a
synthesized clock, thereby decreasing the peak
amplitudes of its harmonics. This results in
significantly lower system EMI compared to the
typical narrow band signal produced by
oscillators and most clock generators. Lowering
EMI by increasing a signal’s bandwidth is called
“spread spectrum clock generation”.
CLKIN
VDD
1
2
3
8
7
6
5
PD#
NC
P1727X
P1766X
VSS
NC
ModOUT
4
REF
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
1of 6
http://www.pulsecore.com
Preliminary Specification
P1727/66
Figure 2 – P1727/66 Block Diagram
V D D
P D #
P LL
M odulation
C LK IN
Frequency
D ivider
P hase
D etector
Loop
Filter
O utput
D ivider
V C O
Feedback
D ivider
M odO U T
R E F
P 1727/66 B lock D iagram
V S S
Table 1-Power Down Selection
PD# Spread Spectrum ModOut
PLL
Mode
0
1
N/A
ON
Disabled
Normal
Disabled
Normal
Power Down
Normal
Table 2 Frequency Deviation Selection
P/N
Deviation
-1.25%
-1,75%
-2.50%
-3.50%
P/N
Deviation
+/-0.625%
+/-0.875%
+/-1.25%
+/-1.75%
P1727/66A
P1727/66B
P1727/66C
P1727/66D
P1727/66E
P1727/66F
P1727/66G
P1727/66H
PIN DESCRIPTION
PIN # Name
Type Description
1
2
3
4
5
6
7
8
CLKIN
VDD
VSS
ModOut
REF
N/C
N/C
PD#
I
P
P
O
Connect to externally generated clock signal.
Connect to +3.3V
Ground Connection. Connect to system ground.
Spread Spectrum Clock Output.
Reference output.
No connect
No connect
I
N/C
N/C
I
Pull low to enable Power Down Mode. This pin has an internal pull-up
resistor.
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
2 of 6
http://www.pulsecore.com
Preliminary Specification
P1727/66
Figure 3 – P1727/66 Schematic for notebook VGA application
66 MHz Pixel Clock Input
Tie low to enable power
down mode.
CLKIN
VDD
PD#
NC
1
2
3
8
0.1uF
No Connect
7
6
5
FB
VDD
VSS
NC
REF
4 ModOUT
Reference clock output
P1766A
66 MHz Pixel Clock with
-1.25%frequency deviation
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
3 of 6
http://www.pulsecore.com
Preliminary Specification
P1727/66
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Unit
VDD, VIN
TSTG
Voltage on any pin with respect to GND
Storage Temperature
-0.5 to +7.0
-65 to +125
0 to +70
V
ºC
ºC
TA
Operating Temperature
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
GND – 0.3
-
-
-
0.8
V
V
2.0
-
VDD + 0.3
-35
Input Low Current (100 KΩ input pull-up
resistor on inputs SR0, 1)
Input High Current (100 KΩ input pull-
down resistor on input SSON)
XOUT Output Low Current
(@ 0.4V, VDD = 3.3V)
XOUT Output High Current
(@ 2.5V, VDD = 3.3V)
Output Low Voltage
(VDD=3.3V, IOL = 20 mA)
Output High Voltage
(VDD=3.3V, IOH = 20 mA)
Static Supply Current
Standby Mode
µA
IIH
-
-
35
µA
mA
mA
V
IXOL
IXOH
VOL
VOH
IDD
-
-
3
-
-
3
-
-
-
0.4
-
2.5
-
V
TBD
-
mA
mA
V
ICC
Dynamic Supply Current
Normal Mode (3.3V and 10 pF loading)
Operating Voltage
TBD
fIN-min
TBD
TBD
fIN-typ
3.3
TBD
fIN-max
TBD
VDD
tON
Power Up Time
(First locked clock cycle after power up)
Clock Output Impedance
-
-
0.18
50
-
-
mS
Ω
ZOUT
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min
Typ
-
Max
Unit
MHz
ns
fIN
Input Frequency: P1727-X
P1766-X
Output Rise Time
(measured at 0.8V to 2.0V)
Output Fall Time
20
40
0.7
40
80
1.1
tLH
Note 1
tHL
0.9
0.8
0.6
1.0
ns
Note 1
tJC
(measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
-
-
TBD
55
ps
%
tD
Output Duty Cycle
45
50
Note1: tLH and tHL are measured into a capacitive load of 15pF
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
4 of 6
http://www.pulsecore.com
Preliminary Specification
P1727/66
Figure 6 – Mechanical Package Outline, (8 Pin SOIC)
C
L
INCHES
MILLIMETERS
SYMBOL MIN
NOR MAX MIN NOR MAX
0.057 0.064 0.071 1.45 1.63 1.80
0.004 0.007 0.010 0.10 0.18 0.25
0.053 0.061 0.069 1.35 1.55 1.75
0.012 0.016 0.020 0.51 0.41 0.31
0.004 0.006 0.001 0.10 0.15 0.25
0.186 0.194 0.202 4.72 4.92 5.12
0.148 0.156 0.164 3.75 3.95 4.15
P17xxx
LOT NUMBER
YYWW
A
A1
A2
B
C
D
E
H
a
D
E
0.050 BSC
1.27 BSC
e
0.224 0.236 0.248 5.70 6.00 6.30
0.012 0.020 0.028 0.30 0.50 0.70
H
L
a
A
A2
A1
0°
5°
8°
0°
5°
8°
B
e
Figure 7 – Mechanical Package Outline, (8 Pin TSSOP)
C
INCHES
MILLIMETERS
SYMBOL MIN
NOR MAX MIN NOR MAX
L
-
-
-
0.047
0.006 0.05
-
-
-
1.10
0.15
A
A1
A2
B
0.002
0.031 0.039 0.041 0.80 1.00 1.05
0.007
0.004
H
E
-
-
0.012 0.19
0.008 0.09
-
-
0.30
0.20
C
0.114 0.118 0.122 2.90 3.00 3.10
0.169 0.173 0.177 4.30 4.40 4.50
D
E
e
a
0.026 BSC
0.65 BSC
D
0.244 0.252 0.260 6.20 6.40 6.60
0.018 0.024 0.030 0.45 0.60 0.75
H
L
0°
-
8°
0°
-
8°
a
A
A2
A1
B
e
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
5 of 6
http://www.pulsecore.com
Preliminary Specification
P1727/66
Ordering Information:
X 17XX X- 08 XX
Package
ST=SOIC in Tube
SR=SOIC in Tape and Reel
TT=TSSOP in Tube
TR=TSSOP in Tape and Reel
Device Pin Count
Deviation (%) and Spread Option Identifier
Device Number
Flow
P=Commercial Temperature Range (0°C to 70°C)
I =Industrial Temperature Range (-25°C to 85°C)
Example:
ORDERING INFORMATION
Ordering Number
P1727/66X-08ST
P1727/66X-08SR
P1727/66X-08TT
P1727/66X-08TR
Marking
Package Type
Qty. / Reel
Temperature
0°C TO 70°C
0°C TO 70°C
0°C TO 70°C
0°C TO 70°C
P1727/66X
P1727/66X
P1727/66X
P1727/66X
8 PIN SOIC, TUBE
8 PIN SOIC, TAPE & REEL
8 PIN TSSOP, TUBE
2,500
8 PIN TSSOP, TAPE & REEL 2,500
"Licensed under U.S. Patent Nos. 5,488,627 and 5,631,920"
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
6 of 6
http://www.pulsecore.com
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