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5AGTFB1G431C4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTFB1G431C4N
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Description:   Arria V Device Handbook
File Size :   1787 K    
Page : 82 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
2–27
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks and temperature sensing diode specifications.
Clock Tree Specifications
lists the clock tree specifications for Arria V devices.
Table 2–24. Clock Tree Performance for Arria V Devices—Preliminary
Performance
Unit
Symbol
Global clock and Regional clock
Peripheral clock
–C4 Speed Grade
625
450
–C5, I5 Speed Grade
625
400
–C6 Speed Grade
525
350
MHz
MHz
PLL Specifications
lists the Arria V PLL specifications when operating in both the commercial
junction temperature range (0° to 85°C) and the industrial junction temperature range
(–40° to 100°C).
Table 2–25. PLL Specifications for Arria V Devices—Preliminary
Symbol
f
IN
f
INPFD
f
FINPFD
f
VCO
t
EINDUTY
Parameter
Input clock frequency (–4 speed grade)
Input clock frequency (–5 speed grade)
Input clock frequency (–6 speed grade)
Integer input clock frequency to the PFD
Fractional input clock frequency to the PFD
PLL VCO operating range (–4 speed grade)
PLL VCO operating range (–5 speed grade)
PLL VCO operating range (–6 speed grade)
Input clock or external feedback clock input duty cycle
Output frequency for internal global or regional clock
(–4 speed grade)
f
OUT
Output frequency for internal global or regional clock
(–5 speed grade)
Output frequency for internal global or regional clock
(–6 speed grade)
Output frequency for external clock output (–4 speed grade)
f
OUT_EXT
t
OUTDUTY
t
FCOMP
t
CONFIGPHASE
t
DYCONFIGCLK
Output frequency for external clock output (–5 speed grade)
Output frequency for external clock output (–6 speed grade)
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
Time required to reconfigure phase shift
Dynamic Configuration Clock
(Part 1 of 3)
Min
5
5
5
5
50
600
600
600
40
45
Typ
50
Max
670
622
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
325
TBD
1600
1400
1300
60
500
500
400
670
622
500
55
10
TBD
100
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
MHz
February 2012
Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
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