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5AGTFB1G631I4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTFB1G631I4N
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Description:   Arria V Device Handbook
File Size :   1787 K    
Page : 82 Pages
Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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Chapter 1: Overview for the Arria V Device Family
Embedded Memory
Embedded Memory
The Arria V memory blocks are flexible and designed to provide an optimal amount
of small- and large-sized memory arrays. Arria V devices contain two types of
embedded memory blocks:
640-bit MLAB blocks—for wide and shallow memories. You can use up to 25% of
the device LABs as MLAB. The MLAB operates at up to 500 MHz.
10-Kb M10K blocks—for larger memory configurations. The M10K embedded
memory operates at up to 400 MHz.
lists the supported memory configurations for Arria V devices.
Table 1–10. Embedded Memory Block Configuration for Arria V Devices
Memory Block
Depth (bits)
Programmable Widths
x16, x18, or x20
x40 or x32
x20 or x16
x10 or x8
x5 or x4
Dynamic and Partial Reconfiguration
Dynamic reconfiguration enables transceiver data rates or encoding schemes to be
changed dynamically while maintaining data transfer on adjacent transceiver
channels in Arria V devices. Dynamic reconfiguration is ideal for applications
requiring on-the-fly multi-protocol or multi-rate support. You can reconfigure the
PMA, PCS, and PCIe hard IP blocks with dynamic reconfiguration.
Partial reconfiguration allows you to reconfigure part of the device while other
sections remain running. Partial reconfiguration is required in systems where the
uptime is critical because it allows you to make updates or adjust functionality
without disrupting other services. While lowering power and cost, partial
reconfiguration also increases the effective logic density by removing the necessity to
place the device functions that do not operate simultaneously. Instead, you can store
these functions in external memory and load them as required. This reduces the size
of the required device by allowing multiple applications on a single device, which
saves board space and reduces power consumption.
Altera simplifies the time-intensive task of partial reconfiguration by building the
partial reconfiguration capability on top of the proven incremental compile and
design flow in the Quartus
II software. With this Altera solution, you do not need to
know all the intricate device architecture details to perform a partial reconfiguration.
Partial reconfiguration is supported through the FPP x16 configuration interface. You
can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to
enable partial reconfiguration of both the core and transceiver simultaneously.
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
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