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5AGTFB1G631I4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTFB1G631I4N
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Description:   Arria V Device Handbook
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
2–29
Table 2–25. PLL Specifications for Arria V Devices—Preliminary
Symbol
dK
BIT
k
VALUE
f
RES
Numerator of Fraction
Resolution of VCO frequency (f
INPFD
=100 MHz)
Parameter
Bit number of Delta Sigma Modulator (DSM)
(1)
(Part 3 of 3)
Min
TBD
Typ
24
8388608
5.96
Max
TBD
Unit
bits
Hz
Notes to
(1) Pending silicon characterization.
(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(3) This specification is limited by the lower of the two: I/O f
MAX
or F
OUT
of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.
(5) F
REF
is fIN/N when N = 1.
(6) Peak-to-peak jitter with a probability level of 10
–12
(14 sigma, 99.99999999974404 % confidence level). The output jitter specification applies to
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in
(7) The cascaded PLL specification is only applicable with the following conditions:
a. Upstream PLL: 0.59 MHz
Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which are available in
DSP Block Specifications
lists the Arria V DSP block performance specifications.
Table 2–26. DSP Block Performance Specifications for Arria V Devices—Preliminary
Performance
Mode
–C4
Speed
Grade
370
370
370
310
370
370
370
370
370
310
370
–C5, I5
Speed
Grade
310
310
310
250
310
310
310
310
310
250
310
–C6
Speed
Grade
220
220
220
200
220
220
220
220
220
200
220
Unit
Modes using One DSP Block
Independent 9 x 9 Multiplication
Independent 18 x 19 Multiplication
Independent 18 x 18 Multiplication
Independent 27 x 27 Multiplication
Independent 18 x 25 Multiplication
Independent 20 x 24 Multiplication
Two 18 x 19 Multiplier Adder Mode
18 x 18 Multiplier Added Summed with 36-bit Input
Modes using Two DSP Blocks
Complex 18 x 19 multiplication
Two 27 x 27 Multiplier Adder
Four 18 x 19 Multiplier Adder
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
February 2012
Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
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