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JVE75A  JVE75B  JVM1812S220T402  
5AGTFD3G427C4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTFD3G427C4N
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Description:   Arria V Device Handbook
File Size :   1787 K    
Page : 82 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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2–28
Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Table 2–25. PLL Specifications for Arria V Devices—Preliminary
Symbol
t
LOCK
t
DLOCK
Parameter
(1)
(Part 2 of 3)
Min
10
Typ
0.3
1.5
4
Max
1
1
±50
0.15
+750
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ms
ms
MHz
MHz
MHz
ps
ns
UI (p-p)
ps (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
%
Time required to lock from end-of-device configuration or
deassertion of
areset
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
f
CLBW
t
PLL_PSERR
t
ARESET
t
INCCJ
Accuracy of PLL phase shift
Minimum pulse width on the
areset
signal
Input clock cycle-to-cycle jitter (F
REF
100 MHz)
Input clock cycle-to-cycle jitter (F
REF
< 100 MHz)
t
OUTPJ_DC
Period jitter for dedicated clock output (F
OUT
100 MHz)
Period jitter for dedicated clock output (F
OUT
< 100 MHz)
Cycle-to-cycle jitter for dedicated clock output
(F
OUT
100 MHz)
Cycle-to-cycle jitter for dedicated clock output
(F
OUT
< 100 MHz)
Period Jitter for clock output on the regular I/O
(F
OUT
100 MHz)
Period Jitter for clock output on the regular I/O
(F
OUT
< 100 MHz)
t
OUTCCJ_DC
t
OUTPJ_IO
t
OUTCCJ_IO
Cycle-to-cycle jitter for clock output on the regular I/O
(F
OUT
100 MHz)
Cycle-to-cycle jitter for clock output on the regular I/O
(F
OUT
< 100 MHz)
Period jitter for dedicated clock output in fractional mode
Cycle-to-cycle jitter for dedicated clock output in fractional
mode
Period Jitter for clock output on the regular I/O in fractional
mode
Cycle-to-cycle jitter for clock output on the regular I/O in
fractional mode
Period jitter for dedicated clock output in cascaded PLLs
(F
OUT
≥100
MHz)
Period jitter for dedicated clock output in cascaded PLLs
(F
OUT
< 100 MHz)
Frequency drift after PFDENA is disabled for a duration of
100 µs
t
OUTPJ_DC_F
t
OUTCCJ_DC_F
t
OUTPJ_IO_F
t
OUTCCJ_IO_F
TBD
TBD
TBD
TBD
TBD
TBD
t
CASC_OUTPJ_DC
t
DRIFT
±10
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
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