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5AGTFD3G427C4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTFD3G427C4N
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Description:   Arria V Device Handbook
File Size :   1787 K    
Page : 82 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
2–35
shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate less than 1.25 Gbps.
Figure 2–3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
baud/1667
20 MHz
DQS Logic Block and Memory Output Clock Jitter Specifications
lists the DQS phase shift error for Arria V devices.
Table 2–32. DQS Phase Shift Error Specification for DLL-Delayed Clock (t
DQS_PSERR
) for Arria V
Devices—Preliminary
Number of DQS Delay
Buffer
2
Notes to
(1) The numbers are preliminary pending silicon characterization.
(2) This error specification is the absolute maximum and minimum error. For example, skew on two DQS delay buffers
in a –4 speed grade is 58 ps or ±29 ps.
–C4
Speed Grade
57
–C5, I5
Speed Grade
58
–C6
Speed Grade
74
Unit
ps
lists the memory output clock jitter specifications for Arria V devices.
Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary
Clock
Network
Regional
Regional
Regional
Global
Global
–4
Speed Grade
Min
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Clock period jitter
Cycle-to-cycle period jitter
t
JIT(per)
t
JIT(cc)
t
JIT(duty)
t
JIT(per)
t
JIT(cc)
–50
–100
–50
–75
–150
Max
50
100
50
75
150
–5
Speed Grade
Min
–55
–110
–82.5
–82.5
–165
Max
55
110
82.5
82.5
165
(Part 1 of 2)
–6
Speed Grade
Min
–55
–110
–82.5
–82.5
–165
Max
55
110
82.5
82.5
165
ps
ps
ps
ps
ps
Parameter
Symbol
Unit
February 2012
Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
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