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5AGTMB1D627C4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTMB1D627C4N
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Description:   Arria V Device Handbook
File Size :   1787 K    
Page : 82 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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Chapter 1: Overview for the Arria V Device Family
Arria V Family Plan
1–5
Table 1–3. Maximum Resource Counts for Arria V GT, SX, and ST Devices—Preliminary
Arria V GT Device
Feature
5AGTD3
ALMs
LE (K)
M10K memory blocks
MLAB memory (Kb)
Block memory (Kb)
Variable-precision DSP blocks
18 x 19 multipliers
FPGA Fractional PLLs
HPS PLLs
FPGA GPIO
HPS I/O
LVDS TX
LVDS RX
PCIe hard IP blocks
Hard memory controllers
HPS memory controllers
ARM Cortex–A9 MPCore
processor
Notes to
(1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs,
when not used by the transceiver I/O, can be used as a general-purpose fractional PLL.
(2) For the LVDS channels count for each package, refer to the
chapter.
Arria V SX Device
5ASXB3
132,075
350
1,729
2,014
17,288
809
1,618
TBD
TBD
528
216
120
120
2
3
1
Dual-core
5ASXB5
174,340
462
2,282
2,658
22,820
1,068
2,186
TBD
TBD
528
216
120
120
2
3
1
Dual-core
Arria V ST Device
5ASTD3
132,075
350
1,729
2,014
17,288
809
1,618
TBD
TBD
528
216
120
120
2
3
1
Dual-core
5ASTD5
174,340
462
2,282
2,658
22,820
1,068
2,186
TBD
TBD
528
216
120
120
2
3
1
Dual-core
5AGTD7
190,240
504
2,414
2,906
24,140
1,156
2,312
16
704
160
176
2
4
136,880
362
1,726
2,098
17,260
1,045
2,090
12
704
160
176
2
4
February 2012
Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
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