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EB2065-CB  EB2065P-BH  EB2065-H-J50  EB2065G-H-J50  EB2065-CC  EB2065-H-J40  EB2065G-CG  EB2065G-CE  EB2065-E-J40  EB2065-E-J30  
5AGTMB1G627C4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTMB1G627C4N
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Description:   Arria V Device Handbook
File Size :   1787 K    
Page : 82 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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2–36
Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary
Clock
Network
Global
–4
Speed Grade
Min
Duty cycle jitter
Note to
(1)
(Part 2 of 2)
–6
Speed Grade
Min
–90
Max
90
ps
Parameter
Symbol
–5
Speed Grade
Min
–90
Max
90
Unit
Max
75
t
JIT(duty)
–75
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
OCT Calibration Block Specifications
lists the OCT calibration block specifications for Arria V devices.
Table 2–34. OCT Calibration Block Specifications for Arria V Devices—Preliminary
Symbol
OCTUSRCLK
T
OCTCAL
T
OCTSHIFT
T
RS_RT
Description
Clock required by OCT calibration blocks
Number of OCTUSRCLK clock cycles required for
R
S
OCT /R
T
OCT calibration
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
Time required between the
dyn_term_ctrl
and
oe
signal
transitions in a bidirectional I/O buffer to dynamically switch
between R
S
OCT and R
T
OCT
Min
Typ
1000
32
Max
20
Unit
MHz
Cycles
Cycles
2.5
ns
shows the T
RS_RT
for
dyn_term_ctrl
and
oe
signals.
Figure 2–4. Timing Diagram for dyn_term_ctrl and oe Signals
RX
Tristate
Tristate
RX
oe
dyn_term_ctrl
T
RS_RT
T
RS_RT
Duty Cycle Distortion (DCD) Specifications
lists the worst-case DCD for Arria V devices.
Table 2–35. Worst-Case DCD on Arria V I/O Pins—Preliminary
–C4 Speed Grade
Symbol
Min
Output Duty Cycle
45
Max
55
–C5,I5 Speed
Grade
Min
45
Max
55
–C6 Speed
Grade
Min
45
Max
55
%
Unit
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
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