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X5168V14I  X5168PIZ-2.7  X5168P-2.7A  X5168V14-2.7A  X5168V14IZ-2.7  X5168S8I  X5168P  X5168V14Z-4.5A  X5168S8I-2.7A  X5168V14I-4.5A  
5AGTMB1G627C4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTMB1G627C4N
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Description:   Arria V Device Handbook
File Size :   1787 K    
Page : 82 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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2–38
Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
FPP Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Arria V devices.
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different
DCLK-to-DATA[]
ratio when you turn on
encryption or the compression feature.
lists the
DCLK-to-DATA[]
ratio for each combination.
Table 2–38. DCLK-to-DATA[] Ratio for Arria V Devices
Configuration Scheme
Encryption
Off
FPP (8-bit wide)
On
Off
On
Off
FPP (16-bit wide)
On
Off
On
Note to
(1) Depending on the
DCLK-to-DATA[]
ratio, the host must send a
DCLK
frequency that is r times the
DATA[]
rate in
byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the
DCLK
frequency
must be 2 times the
DATA[]
rate in Wps.
Compression
Off
Off
On
On
Off
Off
On
On
DCLK-to-DATA[] ratio (r)
1
1
2
2
1
2
4
4
FPP Configuration Timing when DCLK to DATA[] = 1
shows the timing waveform for a FPP configuration when using a MAX
®
II
device as an external host. This timing waveform shows timing when the
DCLK-to-
DATA[]
ratio is 1.
1
When you enable decompression or the design security feature, the
DCLK-to-DATA[]
ratio varies for FPP x8 and FPP x16. For the respective
DCLK-to-DATA[]
ratio, refer to
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
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