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5AGTMB1G627C4N Arria V Device Handbook
Prototype PCB
Part No.:   5AGTMB1G627C4N
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Description:   Arria V Device Handbook
File Size :   1787 K    
Page : 82 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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2–44
Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
lists the internal clock frequency specification for the AS configuration
scheme.
Table 2–42. DCLK Frequency Specification in the AS Configuration Scheme—Preliminary
Minimum
5.3
10.6
21.3
42.6
Notes to
(1) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source.
(2) The AS multi-device configuration scheme does not support
DCLK
frequency of 100 MHz.
Typical
7.9
15.7
31.4
62.9
Maximum
12.5
25.0
50.0
100.0
Unit
MHz
MHz
MHz
MHz
PS Configuration Timing
shows the timing waveform for a passive serial (PS) configuration when
using a MAX II device or microprocessor as an external host.
Figure 2–8. PS Configuration Timing Waveform
t
CF2ST1
t
CFG
nCONFIG
t
CF2CK
nSTATUS
(2)
t
STATUS
t
CF2ST0
t
t
CF2CD
t
ST2CK
(6)
CLK
CONF_DONE
(3)
t
CH
t
CL
(4)
t
DH
(5)
Bit
n
DCLK
DATA0
Bit 0 Bit 1 Bit 2 Bit 3
t
DSU
User I/O
High-Z
User Mode
INIT_DONE
(7)
t
CD2UM
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode,
nCONFIG, nSTATUS,
and
CONF_DONE
are at logic high levels. When
nCONFIG
is pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds
nSTATUS
low for the time of the POR delay.
(3) After power up, before and during configuration,
CONF_DONE
is low.
(4) Do not leave
DCLK
floating after configuration. You can drive it high or low, whichever is more convenient.
(5)
DATA0
is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the
Device and Pins
Option.
(6) To ensure a successful configuration, send the entire configuration data to the Arria V device.
CONF_DONE
is released high after the Arria V device
receives all the configuration data successfully. After
CONF_DONE
goes high, send two additional falling edges on
DCLK
to begin initialization
and enter user mode.
(7) After the option bit to enable the
INIT_DONE
pin is configured into the device, the
INIT_DONE
goes low.
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
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