Chapter 2: Device Datasheet for Arria V Devices
lists the internal clock frequency specification for the AS configuration
Table 2–42. DCLK Frequency Specification in the AS Configuration Scheme—Preliminary
(1) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source.
(2) The AS multi-device configuration scheme does not support
frequency of 100 MHz.
PS Configuration Timing
shows the timing waveform for a passive serial (PS) configuration when
using a MAX II device or microprocessor as an external host.
Figure 2–8. PS Configuration Timing Waveform
Bit 0 Bit 1 Bit 2 Bit 3
(1) The beginning of this waveform shows the device in user mode. In user mode,
are at logic high levels. When
is pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds
low for the time of the POR delay.
(3) After power up, before and during configuration,
(4) Do not leave
floating after configuration. You can drive it high or low, whichever is more convenient.
is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the
Device and Pins
(6) To ensure a successful configuration, send the entire configuration data to the Arria V device.
is released high after the Arria V device
receives all the configuration data successfully. After
goes high, send two additional falling edges on
to begin initialization
and enter user mode.
(7) After the option bit to enable the
pin is configured into the device, the
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
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