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5CSTD6 Cyclone V Device Handbook
Prototype PCB
Part No.:   5CSTD6
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Description:   Cyclone V Device Handbook
File Size :   1776 K    
Page : 74 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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1–6
Chapter 1: Overview for Cyclone V Device Family
Cyclone V Family Plan
Table 1–5. Maximum Resource Counts for Cyclone V SX and ST Devices—Preliminary
(Part 2 of 2)
Cyclone V SX Device
Resource
5CSXC4
PCIe Hard IP Block
FPGA Memory Controller
HPS Memory Controller
ARM Cortex-A9 MPCore Processor
Note to
(1) The maximum FPGA fractional PLLs listed include FPGA general purpose PLLs and transceiver PLLs.
Cyclone V ST Device
5CSXC6
2
1
1
Dual-core
5CSTD5
2
1
1
Dual-core
5CSTD6
2
1
1
Dual-core
5CSXC5
2
1
1
Dual-core
2
1
1
Dual-core
lists the Cyclone V E, GX, and GT package plan that shows the GPIO count,
the maximum number of transceivers available, and the vertical migration capability
for each device package and density.
Table 1–6. Package Plan for Cyclone V E, GX, and GT Devices—Preliminary
F256
(17 mm)
XCVR
GPIO
Device
U324
(15 mm)
XCVR
GPIO
U484
(19 mm)
XCVR
GPIO
F484
(23 mm)
XCVR
GPIO
F672
(27 mm)
XCVR
GPIO
F896
(31 mm)
XCVR
GPIO
F1152
(35 mm)
XCVR
12
12
GPIO
560
560
5CEA2
5CEA4
5CEA5
5CEA7
5CEA9
5CGXC3
5CGXC4
5CGXC5
5CGXC7
5CGXC9
5CGTD5
5CGTD7
5CGTD9
Notes to
144
144
176
176
112
3
288
288
272
240
208
224
224
240
240
240
3
6
6
6
6
6
288
288
272
240
224
208
240
240
240
224
240
240
224
3
6
6
6
6
6
6
6
336
336
336
336
336
336
368
336
336
6
6
9
9
6
9
9
480
448
480
448
480
448
9
12
9
12
(1) The arrows indicate the package vertical migration capability. You can also migrate your design across device densities in the same packaging
option if the devices have the same dedicated pins, configuration pins, and power pins.
(2) The transceiver counts listed are for 3-Gbps transceivers.
(3) The transceiver counts listed are for 5-Gbps transceivers.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
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