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5CSTD6 Cyclone V Device Handbook
Prototype PCB
Part No.:   5CSTD6
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Description:   Cyclone V Device Handbook
File Size :   1776 K    
Page : 74 Pages
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Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
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Chapter 1: Overview for Cyclone V Device Family
Cyclone V Features Summary
1–3
Table 1–1. Summary of Features for Cyclone V Devices (Part 2 of 2)
Feature
Details
Dual-core ARM Cortex-A9 MPCore processor—up to 800 MHz maximum frequency with support
for symmetric and asymmetric multiprocessing
Interface peripherals—10/100/1000 Ethernet media access control (MAC), USB 2.0 On-The-GO
(OTG) controller, serial peripheral interface (SPI), Quad SPI flash controller, NAND flash controller,
SD/MMC/SDIO controller, UART, controller area network (CAN), I2C interface, and up to 71 HPS I/O
interfaces
System peripherals—general-purpose and watchdog timers, direct memory access (DMA)
controller, FPGA configuration manager, and clock and reset managers
On-chip RAM and boot ROM
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA
bridges that allow the FPGA fabric to master transactions to slaves in the HPS, and vice versa.
FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport
front end (MPFE) of the HPS SDRAM controller
ARM CoreSight
JTAG debug access port, trace port, and on-chip trace storage
HPS
(Cyclone V SE, SX,
and ST devices
only)
High-performance
FPGA fabric
Internal memory
blocks
Phase-locked
loops (PLLs)
Enhanced 8-input ALM with four registers
M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25% of
the ALMs as MLAB memory
Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
Integer mode and fractional mode
550 MHz global clock network
Global, quadrant, and peripheral clock networks
Clock networks that are not used can be powered down to reduce dynamic power
Partial and dynamic reconfiguration of the FPGA
CvP
Active serial (AS) x1 and x4, fast passive parallel (FPP) x8 and x16, passive serial (PS), and JTAG
options
Enhanced advanced encryption standard (AES) design security features
Tamper protection
Wirebond low-halogen packages
Multiple device densities with compatible package footprints for seamless migration between
different device densities
RoHS-compliant options
Clock networks
Configuration
Packaging
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
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