Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
shows the LVPECL DC-coupled termination.
Figure 7–9. LVPECL DC-Coupled Termination
Cyclone III Device Family
Differential SSTL I/O Standard Support in the Cyclone III Device Family
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. The Cyclone III device family supports
differential SSTL-2 and SSTL-18 I/O standards. The differential SSTL output standard
is only supported at
pins using two single-ended SSTL output buffers
with the second output programmed to have
opposite polarity. The differential SSTL input standard is supported on the GCLK
pins only, treating differential inputs as two single-ended SSTL and only decoding
one of them.
The differential SSTL I/O standard requires two differential inputs with an external
reference voltage (VREF) as well as an external termination voltage (VTT) of 0.5 × V
to which termination resistors are connected.
For more information about the differential SSTL electrical specifications, refer to the
chapter and the
shows the differential SSTL Class I interface.
Figure 7–10. Differential SSTL Class I Interface
Cyclone III Device Handbook
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