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CLK15_6P Cyclone III Device Handbook
Prototype PCB
Part No.:   CLK15_6P
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Description:   Cyclone III Device Handbook
File Size :   7302 K    
Page : 274 Pages
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8–12
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Features
DDR Output Registers
A dedicated write DDIO block is implemented in the DDR output and output enable
paths.
shows how Cyclone III device family dedicated write DDIO block is
implemented in the I/O element (IOE) registers.
Figure 8–5. Cyclone III Device Family Dedicated Write DDIO
DDR Output Enable Registers
Output Enable
IOE
Register
Output Enable
Register A
OE
data1
data0
IOE
Register
Output Enable
Register B
OE
DDR Output Registers
datain_l
IOE
Register
data0
Output Register A
O
data1
DQ or DQS
datain_h
IOE
Register
-90° Shifted Clock
Output Register B
O
®
The two DDR output registers are located in the I/O element (IOE) block. Two serial
data streams routed through
datain_l
and
datain_h,
are fed into two registers,
output register Ao
and
output register Bo,
respectively, on the same clock edge.
The output from
output register Ao
is captured on the falling edge of the clock, while
the output from
output register Bo
is captured on the rising edge of the clock. The
registered outputs are multiplexed by the common clock to drive the DDR output pin
at twice the data rate.
The DDR output enable path has a similar structure to the DDR output path in the
IOE block. The second output enable register provides the write preamble for the
DQS
strobe in DDR external memory interfaces. This active-low output enable register
extends the high-impedance state of the pin by half a clock cycle to provide the
external memory’s
DQS
write preamble time specification.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
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