Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
The output resistance of the repeater buffers must fit the maximum overshoot
equation shown in
is the transmission line impedance and R
is the equivalent resistance of the output buffer.
This section describes the configuration process.
For more information about the configuration cycle state machine of Altera
refer to the
chapter in volume 1 of the
If the device is powered up from the power-down state, the V
for all the I/O
banks must be powered up to the appropriate level for the device to exit POR.
To begin configuration, the required voltages listed in
must be powered up
to the appropriate voltage levels.
Table 9–4. Power-Up Voltage for Cyclone III Device Family Configuration
Cyclone III LS
(1) Voltages must be powered up to the appropriate voltage levels to begin configuration.
is for banks in which the configuration and JTAG pins reside.
Voltage that must be Powered-Up
is low, the device is in reset. After power-up, the Cyclone III
device family goes through POR. POR delay depends on the MSEL pin settings,
which correspond to your configuration scheme.
Depending on the configuration scheme, a fast or standard POR time is available.
POR time for fast POR ranges between 3–9 ms. POR time for standard POR, which
has a lower power-ramp rate, ranges between 50–200 ms.
During POR, the device resets, holds
low, and tri-states all
user I/O pins.
The configuration bus is not tri-stated in POR stage if the
pins are set to AS or AP
mode. To tri-state the configuration bus for AS and AP configuration schemes, you
low. For more information about the hardware
implementation, refer to
Cyclone III Device Handbook
August 2012 Altera Corporation
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