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DIFFCLK_1N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1N
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Description:   Cyclone III Device Handbook
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Page : 274 Pages
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Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
7–9
shows a typical BLVDS topology with multiple transmitter and receiver
pairs.
Figure 7–4. BLVDS Topology with Cyclone III Device Family Transmitters and Receivers
V
CC
100 kΩ
50
Ω
R
T
50
Ω
100 kΩ
50
Ω
50
Ω
50
Ω
50
Ω
GND
R
S
R
S
R
S
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
100 k
Ω
GND
R
S
50
Ω
50
Ω
50
Ω
R
T
V
CC
100 kΩ
R
S
Cyclone III Device Family
Cyclone III Device Family
R
S
Output
Data
Input
Data
Output
Data
Input
Data
Output
Data
Input
Data
The BLVDS I/O standard is supported on all I/O banks of the Cyclone III device
family. The BLVDS transmitter uses two single-ended output buffers with the second
output buffer programmed as inverted, while the BLVDS receiver uses a true LVDS
input buffer. The transmitter and receiver share the same pins. An output-enabled (OE)
signal is required to tristate the output buffers when the LVDS input buffer receives a
signal.
f
For more information about BLVDS I/O features and electrical specifications, refer to
the
chapter in volume 1 of the
Cyclone III
Device Handbook
and the
and
chapters.
f
For more information and design examples about implementing the BLVDS interfaces
in the Cyclone III device family, refer to
Designing with BLVDS
The BLVDS bidirectional communication requires termination at both ends of the bus
in BLVDS. The termination resistor (R
T
) must match the bus differential impedance,
which in turn depends on the loading on the bus. Increasing the load decreases the
bus differential impedance. With termination at both ends of the bus, termination is
not required between the two signals at the input buffer. A single series resistor (R
S
) is
required at the output buffer to match the output buffer impedance to the
transmission line impedance. However, this series resistor affects the voltage swing at
the input buffer. The maximum data rate achievable depends on many factors.
1
Altera recommends that you perform simulation using the IBIS model while
considering factors such as bus loading, termination values, and output and input
buffer location on the bus to ensure that the required performance is achieved.
December 2011
Altera Corporation
Cyclone III Device Family
OE
OE
OE
Cyclone III Device Handbook
Volume 1
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