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DIFFCLK_1N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1N
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Description:   Cyclone III Device Handbook
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Page : 274 Pages
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11–6
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Error Detection Timing
lists the minimum and maximum error detection frequencies.
Table 11–5. Minimum and Maximum Error Detection Frequencies
Device Type
Cyclone III
device family
Error
Detection
Frequency
80 MHz/2
n
Maximum Error
Detection
Frequency
80 MHz
Minimum Error
Detection
Frequency
312.5 kHz
Valid Divisors (2
)
0, 1, 2, 3, 4, 5, 6, 7, 8
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (for more information, refer to
The
divisor is a power of two (2), where
n
is between 0 and 8. The divisor ranges from one
through 256. Refer to
Equation 11–1. Error Detection Frequency
80 MHz
Error detection frequency
=
--------------------
-
n
2
CRC calculation time depends on the device and the error detection clock frequency.
lists the estimated time for each CRC calculation with minimum and
maximum clock frequencies for Cyclone III device family.
Table 11–6. CRC Calculation Time
Device
EP3C5
EP3C10
EP3C16
Cyclone III
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
EP3CLS70
Cyclone III LS
EP3CLS100
EP3CLS150
EP3CLS200
Notes to
(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different
processes, voltages, and temperatures (PVT).
(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.
Minimum Time (ms)
5
5
7
9
15
23
31
45
42
42
79
79
Maximum Time (s)
2.29
2.29
3.17
4.51
7.48
11.77
15.81
22.67
21.24
21.24
40.27
40.27
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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