Chapter 11: SEU Mitigation in the Cyclone III Device Family
For Cyclone III LS devices, the “Enable
Open Drain on CRC Error Pin”
option is not
available because the Quartus II software sets the
pin for the Cyclone III LS
device as open drain output by default.
Accessing Error Detection Block Through User Logic
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit
register. This signature is read out by user logic from the core. The
primitive is a WYSIWYG component used to establish the
interface from user logic to the error detection circuit. The
primitive atom contains the input and output ports that must be included in the atom.
To access the logic array, the
WYSIWYG atom must be
inserted into your design.
shows the error detection block diagram in FPGA devices and shows the
interface that the WYSIWYG atom enables in your design.
Figure 11–3. Error Detection Block Diagram
Internal Chip Oscillator
(1 to 256 Factor)
(Shown in BIDIR Mode)
(Saved in the Option Register)
The user logic is affected by the soft error failure, thus reading out the 32-bit CRC
signature through the
should not be relied upon to detect a soft error. You
should rely on the
output signal itself, because this
signal cannot be affected by a soft error.
To enable the
WYSIWYG atom, you must name the atom for each
Cyclone III device family accordingly.
Cyclone III Device Handbook
December 2011 Altera Corporation
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