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DIFFCLK_1N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1N
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Description:   Cyclone III Device Handbook
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Page : 274 Pages
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2–4
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Logic Array Blocks
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, and
comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry
chain (Figure
LEs in arithmetic mode can drive out registered and unregistered
versions of the LUT output. Register feedback and register packing are supported
when LEs are used in arithmetic mode.
shows LEs in arithmetic mode.
Figure 2–3. Cyclone III Device Family LEs in Arithmetic Mode
Packed Register Input
Register Chain
Connection
sload
sclear
(LAB
Wide)
(LAB
Wide)
data4
data1
data2
Three-Input
LUT
D
Q
Row, Column, and
Direct link routing
data3
cin (from cout
of previous LE)
Three-Input
LUT
ENA
CLRN
Row, Column, and
Direct link routing
clock (LAB
Wide)
ena (LAB
Wide)
aclr (LAB
Wide)
Local Routing
cout
Register
Chain Output
Register Bypass
Register Feedback
The Quartus II Compiler automatically creates carry chain logic during design
processing. You can also manually create the carry chain logic during design entry.
Parameterized functions, such as LPM functions, automatically take advantage of
carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 LEs by automatically
linking LABs in the same column. For enhanced fitting, a long carry chain runs
vertically, which allows fast horizontal connections to M9K memory blocks or
embedded multipliers through direct link interconnects. For example, if a design has a
long carry chain in a LAB column next to a column of M9K memory blocks, any LE
output can feed an adjacent M9K memory block through the direct link interconnect.
If the carry chains run horizontally, any LAB which is not next to the column of M9K
memory blocks uses other row or column interconnects to drive a M9K memory
block. A carry chain continues as far as a full column.
Logic Array Blocks
Logic array blocks (LABs) contain groups of LEs.
Topology
Each LAB consists of the following features:
16 LEs
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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