Electronic Components Datasheet Search
English 中文版
Manufacturer Upload
Part Name:
DIFFCLK_1N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1N
Download: Download   Right selection Save Target As
View Datasheet (Html)   No need to install PDF reader software
Description:   Cyclone III Device Handbook
File Size :   7302 K    
Page : 274 Pages
Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
Buy Now :   
  DIFFCLK_1N Datasheet PDF page 18 DIFFCLK_1N Datasheet PDF page 19 DIFFCLK_1N Datasheet PDF page 20 DIFFCLK_1N Datasheet PDF page 21 DIFFCLK_1N Datasheet PDF page 23 DIFFCLK_1N Datasheet PDF page 24 DIFFCLK_1N Datasheet PDF page 25 DIFFCLK_1N Datasheet PDF page 26  
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Architecture
The hot socketing feature allows you to use FPGAs on PCBs that also contain a
mixture of 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. The Cyclone III device family
hot socketing feature eliminates power-up sequence requirements for other devices
on the board for proper FPGA operation.
For more information about hot socketing and power-on-reset, refer to the
SEU Mitigation
Cyclone III LS devices offer built-in error detection circuitry to detect data corruption
due to soft errors in the CRAM cells. This feature allows CRAM contents to be read
and verified to match a configuration-computed CRC value. The Quartus II software
activates the built-in 32-bit CRC checker, which is part of the Cyclone III LS device.
For more information about SEU mitigation, refer to the
JTAG Boundary Scan Testing
Cyclone III device family supports the JTAG IEEE Std. 1149.1 specification. The
boundary-scan test (BST) architecture offers the capability to test pin connections
without using physical test probes and captures functional data while a device is
operating normally. Boundary-scan cells in the Cyclone III device family can force
signals onto pins or capture data from pins or from logic array signals. Forced test
data is serially shifted into the boundary-scan cells. Captured data is serially shifted
out and externally compared to expected results. In addition to BST, you can use the
IEEE Std. 1149.1 controller for the Cyclone III LS device in-circuit reconfiguration
For more information about JTAG boundary scan testing, refer to the
Quartus II Software Support
The Quartus II software is the leading design software for performance and
productivity. It is the only complete design solution for CPLDs, FPGAs, and ASICs in
the industry. The Quartus II software includes an integrated development
environment to accelerate system-level design and seamless integration with leading
third-party software tools and flows.
The Cyclone III LS devices provide both physical and functional separation between
security critical design partitions. Cyclone III LS devices offer isolation between
design partitions. This ensures that device errors do not propagate from one partition
to another, whether unintentional or intentional. The Quartus II software design
separation flow facilitates the creation of separation regions in Cyclone III LS devices
by tightly controlling the routing in and between the LogicLock regions. For ease of
use, the separation flow integrates in the existing incremental compilation flow.
For more information about the Quartus II software features, refer to the
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Home - IC Supply - Link
Copyright© 2001 - 2014 ICPDF All Rights Reserved ICPDF.COM

粤公网安备 44030402000629号