Chapter 3: Memory Blocks in the Cyclone III Device Family
The clock-enable control signal controls the clock entering the input and output
registers and the entire M9K memory block. This signal disables the clock so that the
M9K memory block does not see any clock edges and does not perform any
control signals control the read and write operations for each port
of M9K memory blocks. You can disable the
signals independently to
save power whenever the operation is not required.
shows how the register clock, clear, and control signals are implemented in
the Cyclone III device family M9K memory block.
Figure 3–1. M9K Control Signal Selection
Parity Bit Support
Parity checking for error detection is possible with the parity bit along with internal
logic resources. The Cyclone III device family M9K memory blocks support a parity
bit for each storage byte. You can use this bit as either a parity bit or as an additional
data bit. No parity function is actually performed on this bit.
Cyclone III Device Handbook
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