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DIFFCLK_1N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1N
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Description:   Cyclone III Device Handbook
File Size :   7302 K    
Page : 274 Pages
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3–4
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Byte Enable Support
The Cyclone III device family M9K memory blocks support byte enables that mask
the input data so that only specific bytes of data are written. The unwritten bytes
retain the previous written value. The
wren
signals, along with the byte-enable
(byteena) signals, control the write operations of the RAM block. The default value of
the
byteena
signals is high (enabled), in which case writing is controlled only by the
wren
signals. There is no clear port to the
byteena
registers. M9K blocks support byte
enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.
Byte enables operate in one-hot manner, with the LSB of the
byteena
signal
corresponding to the least significant byte of the data bus. For example, if
byteena = 01
and you are using a RAM block in ×18 mode,
data[8..0]
is enabled
and
data[17..9]
is disabled. Similarly, if
byteena = 11,
both
data[8..0]
and
data[17..9]
are enabled. Byte enables are active high.
lists the byte selection.
Table 3–2. byteena for Cyclone III Device Family M9K Blocks
byteena[3..0]
datain
×
16
[0] = 1
[1] = 1
[2] = 1
[3] = 1
Note to
(1) Any combination of byte enables is possible.
Affected Bytes
datain
×
18
[8..0]
[17..9]
datain
×
32
[7..0]
[15..8]
[23..16]
[31..24]
datain
×
36
[8..0]
[17..9]
[26..18]
[35..27]
[7..0]
[15..8]
shows how the
wren
and
byteena
signals control the RAM operations.
Figure 3–2. Cyclone III Device Family byteena Functional Waveform
inclock
wren
rden
address
data
byteena
contents at a0
contents at a1
contents at a2
q (asynch)
doutn
an
XXXX
XX
FFFF
FFFF
FFFF
ABFF
FFCD
ABCD
ABFF
10
a0
a1
ABCD
01
11
ABFF
FFCD
ABCD
FFCD
ABCD
a2
a0
a1
XXXX
XX
a2
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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