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DIFFCLK_1N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1N
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Description:   Cyclone III Device Handbook
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Page : 274 Pages
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Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
3–5
Figure 3–2. Cyclone III Device Family byteena Functional Waveform
Note to
(1) For this functional waveform,
New Data
mode is selected.
(1)
When a
byteena
bit is deasserted during a write cycle, the old data in the memory
appears in the corresponding data-byte output. When a
byteena
bit is asserted during
a write cycle, the corresponding data-byte output depends on the setting chosen in
the Quartus
®
II software. The setting can either be the newly written data or the old
data at that location.
Packed Mode Support
Cyclone III device family M9K memory blocks support packed mode. You can
implement two single-port memory blocks in a single block under the following
conditions:
Each of the two independent block sizes is less than or equal to half of the M9K
block size. The maximum data width for each independent block is 18 bits wide.
Each of the single-port memory blocks is configured in single-clock mode. For
more information about packed mode support, refer to
and
Address Clock Enable Support
Cyclone III device family M9K memory blocks support an active-low address clock
enable, which holds the previous address value for as long as the
addressstall
signal
is high (addressstall
= '1').
When you configure M9K memory blocks in dual-port
mode, each port has its own independent address clock enable.
shows an address clock enable block diagram. The address register output
feeds back to its input using a multiplexer. The multiplexer output is selected by the
address clock enable (addressstall) signal.
Figure 3–3. Cyclone III Device Family Address Clock Enable Block Diagram
address[0]
address[0]
register
address[0]
address[N]
addressstall
clock
address[N]
register
address[N]
December 2011
Altera Corporation
Cyclone III Device Handbook
Volume 1
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