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AP431_10  AP432  TX6-104H  
DIFFCLK_1P Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1P
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Description:   Cyclone III Device Handbook
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Page : 274 Pages
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3–12
Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
In true dual-port mode, you can access any memory location at any time from either
port A or port B. However, when accessing the same memory location from both
ports, you must avoid possible write conflicts. When you attempt to write to the same
address location from both ports at the same time, a write conflict happens. This
results in unknown data being stored to that address location. There is no conflict
resolution circuitry built into the Cyclone III device family M9K memory blocks. You
must handle address conflicts external to the RAM block.
shows true dual-port timing waveforms for the write operation at port A
and read operation at port B. Registering the outputs of the RAM simply delays the
q
outputs by one clock cycle.
Figure 3–12. Cyclone III Device Family True Dual-Port Timing Waveforms
clk_a
wren_a
address_a
data_a
rden_a
q_a (asynch)
clk_b
wren_b
address_b
rden_b
q_b (asynch)
doutn-1
doutn
dout0
dout1
dout2
bn
b0
b1
b2
b3
din-1
din
dout0
dout1
dout2
dout3
din4
din5
an-1
din-1
an
din
a0
a1
a2
a3
a4
din4
a5
din5
a6
din6
Shift Register Mode
Cyclone III device family M9K memory blocks can implement shift registers for
digital signal processing (DSP) applications, such as finite impulse response (FIR)
filters, pseudo-random number generators, multi-channel filtering, and
auto-correlation and cross-correlation functions. These and other DSP applications
require local data storage, traditionally implemented with standard flipflops that
quickly exhaust many logic cells for large shift registers. A more efficient alternative is
to use embedded memory as a shift register block, which saves logic cell and routing
resources.
The size of a (w
× m × n)
shift register is determined by the input data width (w), the
length of the taps (m), and the number of taps (n), and must be less than or equal to
the maximum number of memory bits, which is 9,216 bits. In addition, the size of
(w
× n)
must be less than or equal to the maximum width of the block, which is 36 bits.
If you need a larger shift register, you can cascade the M9K memory blocks.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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