Chapter 3: Memory Blocks in the Cyclone III Device Family
Read or Write Clock Mode
Cyclone III device family M9K memory blocks can implement read or write clock
mode for FIFO and simple dual-port memories. In this mode, a write clock controls
the data inputs, write address, and
registers. Similarly, a read clock controls the
data outputs, read address, and
registers. M9K memory blocks support
independent clock enables for both the read and write clocks.
When using read or write mode, if you perform a simultaneous read or write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode, input clock mode, or output
clock mode and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Cyclone III device family M9K memory blocks can implement single-clock mode for
FIFO, ROM, true dual-port, simple dual-port, and single-port memories. In this mode,
you can control all registers of the M9K memory block with a single clock together
with clock enable.
This section describes designing with M9K memory blocks.
describe the functionality of the various RAM
configurations when reading from an address during a write operation at that same
There are two read-during-write data flows: same-port and mixed-port.
shows the difference between these flows.
Figure 3–14. Cyclone III Device Family Read-During-Write Data Flow
Cyclone III Device Handbook
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