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DIFFCLK_1P Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1P
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Description:   Cyclone III Device Handbook
File Size :   7302 K    
Page : 274 Pages
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3–18
Chapter 3: Memory Blocks in the Cyclone III Device Family
Document Revision History
Power-Up Conditions and Memory Initialization
The M9K memory block outputs of the Cyclone III device family power up to zero
(cleared) regardless of whether the output registers are used or bypassed. All M9K
memory blocks support initialization using a
.mif.
You can create
.mifs
in the
Quartus II software and specify their use using the RAM MegaWizard Plug-In
Manager when instantiating memory in your design. Even if memory is
pre-initialized (for example, using a
.mif),
it still powers up with its outputs cleared.
Only the subsequent read after power up outputs the pre-initialized values.
f
For more information about
.mifs,
refer to the
and the
Power Management
The M9K memory block clock enables of the Cyclone III device family allow you to
control clocking of each M9K memory block to reduce AC power consumption. Use
the
rden
signal to ensure that read operations only occur when necessary. If your
design does not require read-during-write, reduce power consumption by deasserting
the
rden
signal during write operations, or any period when there are no memory
operations. The Quartus II software automatically powers down any unused M9K
memory blocks to save static power.
Document Revision History
lists the revision history for this document.
Table 3–6. Document Revision History
Date
December 2011
December 2009
July 2009
Version
2.3
2.2
2.1
Minor text edits.
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
Changes
Updated chapter part number.
Updated “Introduction” on page 3–1.
Updated “Overview” on page 3–1.
Updated Table 3–1 on page 3–2.
Updated “Control Signals” on page 3–3.
Updated “Memory Modes” on page 3–8.
Updated “Simple Dual-Port Mode” on page 3–10.
Updated “Read or Write Clock Mode” on page 3–16.
Revised the maximum performance of the M9K blocks to 315 MHz in “Introduction” and
“Overview” sections, and in Table 3-1.
Updated “Address Clock Enable Support” section.
June 2009
2.0
October 2008
May 2008
July 2007
March 2007
1.3
1.2
Updated chapter to new template.
1.1
1.0
Added chapter TOC and “Referenced Documents” section.
Initial release.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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